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CN-122023553-A - Rendering circuit, chip and electronic equipment

CN122023553ACN 122023553 ACN122023553 ACN 122023553ACN-122023553-A

Abstract

The application discloses a rendering circuit, a chip and electronic equipment, which belong to the technical field of electronic equipment, wherein the rendering circuit comprises a command and control module, a rendering module and a storage and interface module, the command and control module, the rendering module and the storage and interface module are electrically connected, the command and control module is used for receiving instructions, determining a plurality of target image blocks according to an image to be rendered and scheduling the target image blocks, the rendering module is used for rendering the target image blocks scheduled by the command and control module, the rendering module comprises a plurality of rendering sub-modules, each rendering sub-module is used for executing at least one rendering step, when the target image blocks are rendered, the plurality of rendering sub-modules are used for rendering the target image blocks one by one, and the storage and interface module is used for receiving the target image blocks sent by external storage, storing the target image blocks and sending the target image blocks which are rendered by the rendering module to the external storage.

Inventors

  • HUANG GUOQUAN

Assignees

  • 维沃移动通信有限公司

Dates

Publication Date
20260512
Application Date
20260130

Claims (17)

  1. 1. A rendering circuit is characterized by comprising a command and control module, a rendering module and a storage and interface module; the command and control module is electrically connected with the rendering module and the storage and interface module; The command and control module is used for receiving the command, determining a plurality of target image blocks according to the image to be rendered, and scheduling the target image blocks; The system comprises a command and control module, a rendering module, a target image block, a plurality of rendering sub-modules, a control module and a display module, wherein the rendering module is used for rendering the target image block scheduled by the command and control module, and comprises a plurality of rendering sub-modules, each of which is used for executing at least one rendering step; The storage and interface module is used for receiving the target image block sent by the external storage, storing the target image block and sending the target image block rendered by the rendering module to the external storage.
  2. 2. The rendering circuit of claim 1, wherein the rendering circuit is configured to render the rendering data, And the target image block is an image block of a position associated with the interactive interface in the image to be rendered.
  3. 3. The rendering circuit of claim 1, wherein the rendering circuit is configured to render the rendering data, The plurality of rendering sub-modules comprise at least one of a shape and gradient sub-module, an optical processing sub-module, a color matrix sub-module, a blurring processing sub-module, a light shadow processing sub-module and a mixing and synthesizing sub-module; the shape and gradient submodule is used for determining a stable gradient normal of an interaction interface in the target image block; The optical processing submodule is used for carrying out optical simulation of preset materials on the inner area of the interactive interface based on the stable gradient normal; The color matrix submodule is used for carrying out color adjustment on the internal area of the interactive interface after the optical simulation; The blurring processing sub-module is used for carrying out first blurring processing on the internal area of the interaction interface after the color adjustment; The light and shadow processing submodule is used for performing light and shadow simulation on the inner area and the outer area of the interactive interface after the first blurring process; And the mixing and synthesizing submodule is used for mixing the interaction interface after the light and shadow simulation with the bottom image of the target image block.
  4. 4. The rendering circuit of claim 3, wherein the rendering circuit is configured to render the rendering signal, The shape and gradient submodule is used for determining pixel coordinates in the target image block and boundaries of the interactive interface and determining signed distances and a first normal; The shape and gradient sub-module is further configured to determine the stable gradient normal based on the signed distance and the first normal.
  5. 5. The rendering circuit of claim 3, wherein the rendering circuit is configured to render the rendering signal, The optical processing sub-module comprises a refraction and depth unit, a dispersion unit and a penetration unit, and when the target image block is rendered, the refraction and depth unit, the dispersion unit and the penetration unit render the target image block one by one; the refraction and depth unit is used for carrying out light refraction simulation on the internal area of the interaction interface based on the stable gradient normal; The dispersion unit is used for carrying out dispersion simulation on the edge area of the interaction interface after the light refraction simulation; And the penetration unit is used for performing light penetration simulation on the internal area of the interaction interface after dispersion simulation.
  6. 6. The rendering circuit of claim 5, wherein the refraction and depth unit is configured to perform a ray refraction simulation on an interior region of the interaction interface based on the stable gradient normal, comprising: The refraction and depth unit is used for determining the displacement amplitude of the pixel points in the inner area of the interactive interface according to the signed distance, the refraction height and the refraction intensity of the pixel points in the inner area of the interactive interface, wherein the signed distance is determined according to the pixel points in the inner area of the interactive interface and the edges of the interactive interface, and the refraction height and the refraction intensity are parameters of the light refraction simulation; the refraction and depth unit is further used for determining the normal direction of the stable gradient normal according to a center vector, the stable gradient normal and a depth coefficient, wherein the center vector is determined according to pixel points and a preset focus in an inner area of the interactive interface, and the depth coefficient is a parameter of the light refraction simulation; the refraction and depth unit is further used for determining the refraction coordinates of the pixel points in the inner area of the interactive interface according to the displacement amplitude and the normal direction, and drawing the refraction effect.
  7. 7. The rendering circuit of claim 5, wherein the dispersive unit is configured to perform dispersion simulation on an edge region of the interaction interface after the refraction simulation of the light ray, and includes: The dispersion unit is used for determining a plurality of sampling points in the edge area of the interaction interface after the light refraction simulation; the dispersion unit is also used for respectively carrying out accumulated calculation on an R channel, a G channel and a B channel according to a plurality of sampling points; The dispersion unit is also used for carrying out weighted calculation according to the calculation results of the R channel, the G channel and the B channel and drawing dispersion effects.
  8. 8. The rendering circuit of claim 5, wherein the infiltration unit is configured to perform a light ray infiltration simulation on an internal region of the interaction interface after the dispersion simulation, and the rendering circuit comprises: the penetration unit is used for determining the brightness of the internal area of the interaction interface after the dispersion simulation; The penetration unit is also used for carrying out opacity mixing on the brightness of the inner area of the interactive interface and the target color; the infiltration unit is further used for performing second blurring processing on the inner area of the interaction interface after the opacity is mixed according to a preset radius; the penetration unit is also used for synthesizing the fuzzy result after the second fuzzy processing and the refraction result of the light refraction simulation.
  9. 9. A rendering circuit according to claim 3, wherein the shadow processing sub-module comprises a highlight unit and a shadow unit, the highlight unit and the shadow unit rendering the target image block one by one when rendering the target image block; The highlight unit is used for performing highlight reflection simulation on the internal area of the interactive interface after the first blurring process; And the shadow unit is used for carrying out shadow simulation on the external area of the interaction interface after highlight reflection simulation.
  10. 10. The rendering circuit according to any one of claims 1 to 9, wherein the storage and interface module comprises an internal storage sub-module, a handling sub-module and an interface sub-module which are sequentially connected in series, the internal storage sub-module being electrically connected with a plurality of the rendering sub-modules; the internal storage sub-module is electrically connected with the rendering module, and the rendering module is used for rendering the target image block in the internal storage sub-module; The handling sub-module is used for handling the target image block from the external storage to the internal storage sub-module according to the scheduling of the command and control module on the target image block, and is also used for handling the rendered target image block from the internal storage sub-module to the external storage; The interface submodule is used for transmitting the target image block with the external storage.
  11. 11. The rendering circuit of claim 10, wherein the rendering circuit is configured to render the rendering data, The internal storage sub-modules and the carrying sub-modules are respectively provided with two, one internal storage sub-module is electrically connected with one carrying sub-module, and the two internal storage sub-modules are electrically connected; the two internal storage sub-modules and the two carrying sub-modules are used for executing a ping-pong mechanism, so that when the target image block in one internal storage sub-module is rendered, the other internal storage sub-module sends or buffers the target image block.
  12. 12. The rendering circuit of claim 10, wherein the rendering circuit is configured to render the rendering data, The storage and interface module is also used for sending a pattern for sampling to the rendering module.
  13. 13. The rendering circuit of claim 12, wherein the storage and interface module comprises: And the texture sampling sub-module is electrically connected with the rendering module and is used for providing the pattern for the rendering module, and the pattern is determined according to the target image block.
  14. 14. The rendering circuit of any one of claims 1 to 9, wherein the command and control module includes a command front end and an image block scheduler, the command front end and image block scheduler being electrically connected, the image block scheduler and the rendering module being electrically connected; the command front end is used for receiving an instruction; and the image block scheduler is used for scheduling the target image block according to the instruction received by the front end of the command.
  15. 15. The rendering circuit of claim 10, wherein the rendering circuit is configured to render the rendering data, The command and control module is also used for executing clock synchronization and energy consumption management of the rendering module and the storage and interface module.
  16. 16. A chip, comprising: A rendering circuit as claimed in any one of claims 1 to 15.
  17. 17. An electronic device, comprising: Display screen, and The rendering circuit of any one of claims 1 to 15, the display screen and the rendering circuit being electrically connected.

Description

Rendering circuit, chip and electronic equipment Technical Field The application belongs to the technical field of electronic equipment, and particularly relates to a rendering circuit, a chip and electronic equipment. Background Along with the continuous improvement of the display technology of the mobile terminal and the human-computer interaction experience, the visual effect of the interface is evolving from the traditional planarization style to the quasi-physical style such as semitransparent, refractive, soft light and the like. In the related art, rendering of images is dependent on a general-purpose graphics processor (Graphics Processing Unit, GPU), which renders the images to off-screen buffer, and then, after gaussian blurring, color adjustment and semi-transparent superposition, is aided with boundary highlights and shadows. However, these effects are uniformly executed by the graphics processor, and the graphics processor participates in the whole rendering process, so that the whole rendering process is low in efficiency and high in energy consumption. Disclosure of Invention The application aims to provide a rendering circuit, a chip and electronic equipment, which can solve the technical problems of low efficiency and high energy consumption in the rendering process of the electronic equipment. In order to solve the technical problems, the application is realized as follows: In a first aspect, an embodiment of the present application provides a rendering circuit, including a command and control module, a rendering module, and a storage and interface module; the command and control module and the rendering module as well as the storage and interface module are electrically connected; The command and control module is used for receiving the command, determining a plurality of target image blocks according to the image to be rendered, and scheduling the target image blocks; The system comprises a command and control module, a rendering module, a target image block, a plurality of rendering sub-modules, a control module and a control module, wherein the command and control module is used for scheduling the target image block; The storage and interface module is used for receiving the target image block sent by the external storage, storing the target image block, and sending the target image block rendered by the rendering module to the external storage. In a second aspect, an embodiment of the present application proposes a chip, including: Rendering circuitry as provided by embodiments of the first aspect. In a third aspect, an embodiment of the present application provides an electronic device, including: Display screen, and The rendering circuit, the display screen and the rendering circuit are electrically connected as provided in the embodiment of the first aspect. In the embodiment of the application, the rendering circuit comprises a command and control module, a rendering module and a storage and interface module, wherein the command and control module and the rendering module are electrically connected, so that the image blocks are rendered, the command and control module is used for receiving the command, responding to the command, dividing the image to be rendered into a plurality of image blocks (tile), scheduling the target image blocks, and the rendering module can render the target image blocks. The storage and interface module receives the target image block sent by the external storage according to the scheduling of the command and control module, stores the target image block, and the rendering module can render the target image block stored in the storage and interface module, and the storage and interface module can send the rendered target image block to the external storage. The method comprises the steps of generating a target image block, wherein the target image block is subjected to a plurality of rendering sub-modules, each rendering sub-module is used for executing at least one rendering step, and then when the target image block is subjected to rendering, the plurality of rendering sub-modules render the target image block one by one, namely, the plurality of rendering sub-modules are built on hardware according to the rendering steps, each rendering step is executed by one rendering sub-module, so that only after the rendering sub-module finishes rendering the target image block, the next rendering sub-module renders the target image block, and further, a pipelined rendering link is realized, the pipelined rendering link can greatly improve the rendering efficiency compared with the overall execution rendering of a graphic processor, and only one rendering sub-module works at the same time for one target image block, so that the energy consumption can be greatly reduced. Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of