CN-122024608-A - Array substrate, driving method and display device

Abstract

The invention provides an array substrate, a driving method and a display device. The array substrate comprises a substrate and a driving circuit arranged on the substrate, wherein the driving circuit comprises a carry signal providing circuit and N driving signal providing circuits, N is a positive integer, the carry signal providing circuit is used for providing carry signals, the driving signal providing circuit is used for providing driving signals, the carry signal providing circuit and the driving signal providing circuit are arranged along a first direction, the array substrate further comprises scanning lines arranged on the substrate, the driving signal providing circuit is electrically connected with the corresponding scanning lines and used for providing driving signals for the scanning lines, the extending direction of the scanning lines is a second direction, and the first direction is intersected with the second direction. The invention is beneficial to realizing a narrow frame.

Inventors

• ZHAO YUANYANG
• ZHANG XIAOJIE
• WANG SHENG
• ZHU HUAN

Assignees

• 合肥京东方光电科技有限公司
• 京东方科技集团股份有限公司
• 北京京东方技术开发有限公司

Dates

Publication Date

20260512

Application Date

20241112

Claims (20)

1. 1. The array substrate is characterized by comprising a substrate and a driving circuit arranged on the substrate, wherein the driving circuit comprises a carry signal providing circuit and N driving signal providing circuits, wherein N is a positive integer; The carry signal providing circuit is used for providing a carry signal, and the drive signal providing circuit is used for providing a drive signal; the carry signal supply circuit and the drive signal supply circuit are arranged along a first direction; The array substrate further comprises scanning lines arranged on the substrate, wherein the driving signal supply circuit is electrically connected with the corresponding scanning lines and is used for supplying driving signals for the scanning lines; The extending direction of the scanning line is a second direction, and the first direction is intersected with the second direction.
2. 2. The array substrate of claim 1, wherein the carry signal providing circuit comprises a carry output circuit for providing a carry signal according to a carry clock signal under control of a potential of a carry node, and wherein the drive signal providing circuit comprises a drive output circuit for providing a drive signal according to a corresponding drive clock signal under control of a potential of a corresponding drive node; The carry output circuit includes a transistor having a channel width to length ratio that is less than a channel width to length ratio of the drive output circuit.
3. 3. The array substrate of any one of claims 1 or 2, wherein the gate of the transistor included in the carry-out circuit includes p first sub-gates electrically connected to each other, adjacent first sub-gates being electrically connected through a first connection portion; the grid electrode of the transistor included in the driving output circuit comprises m second sub-grid electrodes which are electrically connected with each other, and the adjacent second sub-grid electrodes are electrically connected through a second connecting part; p and m are positive integers, m being greater than p.
4. 4. The array substrate of claim 3, wherein the carry-out circuit comprises at least two first sub-gates having different shapes and/or the carry-out circuit comprises at least two first sub-gates having different sizes, or The drive output circuit includes at least two second sub-gates having different shapes and/or the drive output circuit includes at least two second sub-gates having different sizes.
5. 5. The array substrate according to claim 1 or 2, wherein the carry signal supply circuit further comprises a carry reset circuit for resetting the carry signal under control of a potential of the second node; The carry output circuit comprises a transistor active pattern comprising a first active pattern portion and at least one second active pattern portion; The first active pattern portion is arranged along a first direction with active patterns of transistors included in the carry reset circuit.
6. 6. The array substrate of claim 5, wherein the first active pattern portion and the second active pattern portion are aligned along a second direction.
7. 7. The array substrate of claim 1 or 2, wherein the carry signal providing circuit comprises a carry tank circuit, wherein the carry tank circuit is electrically connected with a carry node and a carry signal output end respectively, and wherein a polar plate of a capacitor included in the carry tank circuit is electrically connected with a corresponding cascade line through a first via hole; The carry tank circuit comprises a capacitor plate with a first avoidance space.
8. 8. The array substrate of claim 7, wherein the carry signal supply circuit includes a first transistor; the first transistor is arranged on one side of the carry energy storage circuit, which is far away from the carry output circuit; the active graph of the first transistor is provided with a second avoiding space so as to avoid the first via hole.
9. 9. The array substrate of claim 8, wherein the first transistor and the carry tank circuit include capacitances aligned along the second direction.
10. 10. The array substrate of claim 8 or 9, wherein the carry signal providing circuit comprises a carry node reset circuit for resetting the potential of the carry node under the control of a reset signal provided by a reset terminal; the carry node reset circuit includes the first transistor.
11. 11. The array substrate of claim 7, wherein the drive signal providing circuit comprises a drive tank circuit, wherein the drive tank circuit is connected with the drive node and the drive signal output terminal respectively; the carry tank circuit may include a capacitor having a different shape than the capacitor included in the drive tank circuit, and/or, The size of the polar plate of the capacitor included in the carry tank circuit is different from the size of the capacitor included in the drive tank circuit.
12. 12. The array substrate according to claim 10, wherein the driving signal supply circuit includes a driving node reset circuit for resetting a potential of the driving node under control of the reset signal; the carry node reset circuit may include transistors having different shapes than the transistors included in the drive node reset circuit, and/or, The carry node reset circuit includes a transistor having a different size than a transistor included in the drive node reset circuit.
13. 13. The array substrate of any one of claims 1 to 9, wherein N is greater than 1; the N driving signal supply circuits include transistors having the same function in the same shape and/or, The N driving signal supply circuits include transistors having the same function and have the same size.
14. 14. The array substrate of claim 1, wherein the carry signal providing circuit comprises a carry node control circuit, a carry node reset circuit, a second node control circuit, a carry output circuit, a carry reset circuit, and a carry tank circuit; The carry node control circuit is respectively and electrically connected with the input end, the second node and the carry node and is used for controlling the potential of the carry node under the control of an input signal provided by the input end and resetting the potential of the carry node under the control of the potential of the second node; The carry node reset circuit is respectively and electrically connected with the reset end and the carry node and is used for resetting the potential of the carry node under the control of a reset signal provided by the reset end; the second node control circuit is respectively and electrically connected with the carry node and the second node and is used for controlling the potential of the second node under the control of the potential of the carry node; the carry output circuit is respectively and electrically connected with the carry node, the carry clock signal end and the carry signal output end and is used for writing a carry clock signal provided by the carry clock signal end into the carry signal output end under the control of the potential of the carry node; The carry reset circuit is respectively and electrically connected with the second node and the carry signal output end and is used for resetting the carry signal provided by the carry signal output end under the control of the potential of the second node; and the carry energy storage circuit is respectively and electrically connected with the carry node and the carry signal output end.
15. 15. The array substrate of claim 1, wherein the nth driving signal providing circuit comprises an nth driving node control circuit, an nth driving node reset circuit, an nth driving output circuit, an nth driving reset circuit, and an nth driving tank circuit, wherein N is a positive integer less than or equal to N; The n-th driving node control circuit is respectively and electrically connected with the input end, the second node and the n-th driving node and is used for controlling the potential of the n-th driving node under the control of an input signal provided by the input end and resetting the potential of the n-th driving node under the control of the potential of the second node; The n-th driving node reset circuit is respectively and electrically connected with the reset end and the n-th driving node and is used for resetting the potential of the n-th driving node under the control of a reset signal provided by the reset end; the nth driving output circuit is respectively and electrically connected with the nth driving node, the nth driving clock signal end and the nth driving signal output end and is used for writing the nth driving clock signal provided by the nth driving clock signal end into the nth driving signal output end under the control of the potential of the nth driving node; the nth driving reset circuit is respectively and electrically connected with the second node and the nth driving signal output end and is used for resetting the nth driving signal provided by the nth driving signal output end under the control of the potential of the second node; The nth driving energy storage circuit is respectively connected with the nth driving node and the nth driving signal output end.
16. 16. The array substrate of claim 1, 2, 3, 4, 5, 6, 7, 8, 9, 14 or 15, comprising a driving module, wherein the driving module is arranged on a first side of a display area and/or a second side of the display area, wherein the first side and the second side are opposite sides; The input end of the a-th driving circuit included in the driving module is electrically connected with the carry signal output end of the a-b-th driving circuit included in the driving module; the reset end of the a-th driving circuit included in the driving module is electrically connected with the carry signal output end of the a+c-th driving circuit included in the driving module; a. b and c are positive integers, and a is less than or equal to A.
17. 17. The array substrate of claim 16, wherein the driving module further comprises a virtual start driving circuit; The virtual initial driving circuit is used for providing corresponding input signals for the input end of the first-stage driving circuit included in the driving module.
18. 18. A driving method applied to the array substrate according to any one of claims 15 to 17, the array substrate including data lines and pixel circuits disposed on a base, wherein a driving period includes a multi-frame display time, the driving method including, in the driving period, Controlling the data voltage on the pixel circuit to be the first polarity data voltage in at least two adjacent frames; Controlling the data voltage on the pixel circuit to be the second polarity data voltage in at least two adjacent frames; The first polarity is opposite the second polarity.
19. 19. The array substrate of claim 16, wherein in the a-th driving circuit, the carry signal providing circuit is electrically connected to the a-th carry clock signal terminal, the N-th driving signal providing circuit is electrically connected to the corresponding driving clock signal terminal, in the a+c-th driving circuit, the carry signal providing circuit is electrically connected to the a+c-th carry clock signal terminal, and N is a positive integer less than or equal to N, the driving method comprises: in the driving period of the a-th driving circuit, N driving clock signal ends electrically connected with the a-th driving circuit sequentially start to output effective driving clock signals; And after the potential of the driving clock signal output by the nth driving clock signal end electrically connected with the a-th driving circuit jumps from the effective voltage to the ineffective voltage, controlling the a+c-th carry clock signal end to provide an effective carry clock signal at intervals of a first preset time.
20. 20. The driving method as claimed in claim 19, wherein the first predetermined time is greater than or equal to 0.5H and less than or equal to 5H, and 1H is a line scanning time.

Description

Array substrate, driving method and display device Technical Field The present invention relates to the field of display technologies, and in particular, to an array substrate, a driving method, and a display device. Background The related display device cannot narrow the lateral frame by arranging the carry signal supply circuit and the drive signal supply circuit while reducing the number of transistors supplied from the drive circuit, which is disadvantageous in realizing the narrow frame. Disclosure of Invention The invention mainly aims to provide an array substrate, a driving method and a display device, and solves the problem that a narrow frame cannot be realized in the related art. In one aspect, an embodiment of the invention provides an array substrate, which comprises a substrate and a driving circuit arranged on the substrate, wherein the driving circuit comprises a carry signal providing circuit and N driving signal providing circuits; The carry signal providing circuit is used for providing a carry signal, and the drive signal providing circuit is used for providing a drive signal; the carry signal supply circuit and the drive signal supply circuit are arranged along a first direction; The array substrate further comprises scanning lines arranged on the substrate, wherein the driving signal supply circuit is electrically connected with the corresponding scanning lines and is used for supplying driving signals for the scanning lines; The extending direction of the scanning line is a second direction, and the first direction is intersected with the second direction. Optionally, the carry signal providing circuit comprises a carry output circuit, wherein the drive signal providing circuit comprises a drive output circuit, the carry output circuit is used for providing a carry signal according to a carry clock signal under the control of the potential of a carry node, and the drive output circuit is used for providing a drive signal according to a corresponding drive clock signal under the control of the potential of a corresponding drive node; The carry output circuit includes a transistor having a channel width to length ratio that is less than a channel width to length ratio of the drive output circuit. Optionally, the gate of the transistor included in the carry output circuit includes p first sub-gates electrically connected to each other, and adjacent first sub-gates are electrically connected through a first connection portion; the grid electrode of the transistor included in the driving output circuit comprises m second sub-grid electrodes which are electrically connected with each other, and the adjacent second sub-grid electrodes are electrically connected through a second connecting part; p and m are positive integers, m being greater than p. Optionally, the carry-out circuit comprises at least two first sub-gates of different shapes and/or the carry-out circuit comprises at least two first sub-gates of different sizes, or The drive output circuit includes at least two second sub-gates having different shapes and/or the drive output circuit includes at least two second sub-gates having different sizes. Optionally, the carry signal providing circuit further includes a carry reset circuit, where the carry reset circuit is configured to reset the carry signal under control of a potential of the second node; The carry output circuit comprises a transistor active pattern comprising a first active pattern portion and at least one second active pattern portion; The first active pattern portion is arranged along a first direction with active patterns of transistors included in the carry reset circuit. Optionally, the first active pattern portion and the second active pattern portion are arranged along a second direction. Optionally, the carry signal providing circuit comprises a carry energy storage circuit, wherein the carry energy storage circuit is respectively and electrically connected with a carry node and a carry signal output end; The carry tank circuit comprises a capacitor plate with a first avoidance space. Optionally, the carry signal providing circuit includes a first transistor; the first transistor is arranged on one side of the carry energy storage circuit, which is far away from the carry output circuit; the active graph of the first transistor is provided with a second avoiding space so as to avoid the first via hole. Optionally, the first transistor and the carry tank circuit include capacitors arranged along the second direction. Optionally, the carry signal providing circuit comprises a carry node resetting circuit, wherein the carry node resetting circuit is used for resetting the potential of the carry node under the control of a reset signal provided by a reset end; the carry node reset circuit includes the first transistor. Optionally, the driving signal providing circuit comprises a driving energy storage circuit, wherein the driving energy storage circuit is respecti