Search

CN-122024613-A - Display panel and display device

CN122024613ACN 122024613 ACN122024613 ACN 122024613ACN-122024613-A

Abstract

The embodiment of the application provides a display panel and a display device, wherein two scanning lines are arranged between two adjacent rows of sub-pixels in the display panel, two columns of sub-pixels are arranged between two adjacent data lines, the sub-pixels positioned in the same column are connected with the same data line, when the display panel is configured into a first display mode, at least two clock signal lines output effective levels to corresponding scanning lines at the same time, at least two scanning lines connected with the at least two clock signal lines are respectively connected with the sub-pixels of different rows, so that the effect of simultaneously starting the sub-pixels of different rows is achieved, and the display panel adopting a DLS strip architecture achieves the effect of a DLG mode.

Inventors

  • YANG SHAOYUAN
  • DAI CHEN

Assignees

  • 广州华星光电半导体显示技术有限公司

Dates

Publication Date
20260512
Application Date
20260317

Claims (10)

  1. 1. The display panel is characterized by comprising a plurality of data lines, a plurality of scanning lines and a plurality of sub-pixels, wherein two scanning lines are arranged between two adjacent rows of the sub-pixels, two columns of sub-pixels are arranged between two adjacent data lines, and the sub-pixels positioned in the same column are connected with the same data line; The display panel further comprises a plurality of clock signal lines, the clock signal lines are respectively and electrically connected with the corresponding scanning lines, when the display panel is configured into a first display mode, at least two clock signal lines simultaneously output effective levels to the corresponding scanning lines, and at least two scanning lines connected with the clock signal lines are respectively connected with the sub-pixels of different rows.
  2. 2. The display panel according to claim 1, wherein the plurality of clock signal lines includes k clock lines, the plurality of scan lines includes nk gate lines arranged in sequence, one of the clock lines is electrically connected to n of the gate lines, and the p-th clock line is electrically connected to the kth (m-1) +p gate line, p is 1≤k, m≤n, k is 4, and p, k, m, and n are positive integers; Wherein, when the display panel is configured in the first display mode, the first clock line and the fourth clock line output the active level to the corresponding scan line simultaneously in the first period.
  3. 3. The display panel according to claim 2, wherein k is equal to 8, and the fifth clock line and the eighth clock line output active levels to the corresponding scan lines simultaneously in the second period of time when the display panel is configured in the first display mode.
  4. 4. The display panel according to claim 3, wherein the second clock line and the third clock line output active levels to the corresponding scan lines, respectively, in a third period of time when the display panel is configured in the first display mode, and the sixth clock line and the seventh clock line output active levels to the corresponding scan lines, respectively, in a fourth period of time.
  5. 5. The display panel according to claim 3, wherein the first, second, third and fourth clock lines output active levels to the corresponding scan lines, respectively, during a first period of time when the display panel is configured in a first display mode, and wherein the fifth, sixth, seventh and eighth clock lines output active levels to the corresponding scan lines, respectively, during a second period of time.
  6. 6. The display panel according to claim 2, wherein k is equal to 16, and when the display panel is configured in the first display mode, each adjacent four of the clock lines output an active level to a corresponding scan line in the same period of time.
  7. 7. The display panel according to claim 2, wherein when the display panel is configured in the first display mode, the first clock line and the fourth clock line output active levels to the corresponding scan lines, respectively, in a first period, the second clock line outputs active levels to the corresponding scan lines in a second period, and the third clock line outputs active levels to the corresponding scan lines in a third period.
  8. 8. The display panel according to claim 7, wherein k is equal to 12, and two clock lines electrically connected to the first gate line and the fourth gate line simultaneously output an active level and clock lines electrically connected to the second gate line and the third gate line sequentially output an active level every four sequentially arranged gate lines when the display panel is configured in the first display mode.
  9. 9. The display panel according to claim 7, wherein k is equal to 12, and when the display panel is configured in the first display mode, the third clock line and the fifth clock line output active levels to the corresponding scan lines, respectively, in a third period, and the eighth clock line outputs active levels to the corresponding scan lines, in a fourth period, and the sixth clock line and the seventh clock line output active levels to the corresponding scan lines, respectively, and in a sixth period, and the ninth clock line outputs active levels to the corresponding scan lines, and in a seventh period, and the twelfth clock line and the tenth clock line output active levels to the corresponding scan lines, respectively.
  10. 10. A display device comprising the display panel according to any one of claims 1 to 9.

Description

Display panel and display device Technical Field The present application relates to the field of display technologies, and in particular, to a display panel and a display device. Background With the development of display technology, in order to improve the refresh rate, DLG (Dual Line Gate) timing is adopted, so that adjacent clock lines in the Gate driving circuit are simultaneously output, thereby reducing the resolution of the product by half and doubling the refresh rate. In order to avoid color mixing, it is necessary to ensure that the same color sub-pixels of adjacent rows are simultaneously turned on, and the display panel carrying the DLG mode is a 1G1D (1 Gate1 Data) strip architecture at present, and in the display panel of the strip architecture of DLS (DATA LINE SHARING ), since two adjacent scanning lines are connected to the same row of pixels, when the DLG timing is adopted, only one row of pixels can still be turned on, and the effect of the DLG mode cannot be achieved. Therefore, when the existing DLG timing sequence is applied to a display panel adopting a DLS strip architecture, the technical problem of the effect of the DLG mode cannot be achieved. Disclosure of Invention The embodiment of the application provides a display panel and a display device, which are used for solving the technical problem that the effect of a DLG mode cannot be realized when the conventional DLG time sequence is applied to the display panel adopting a DLS strip architecture. In order to achieve the above object, according to a first aspect of the present application, there is provided a display panel including a plurality of data lines, a plurality of scan lines, and a plurality of sub-pixels, wherein two scan lines are disposed between two adjacent rows of the sub-pixels, two columns of sub-pixels are disposed between two adjacent data lines, and the sub-pixels located in the same column are connected to the same data line; The display panel further comprises a plurality of clock signal lines, the clock signal lines are respectively and electrically connected with the corresponding scanning lines, when the display panel is configured into a first display mode, at least two clock signal lines simultaneously output effective levels to the corresponding scanning lines, and at least two scanning lines connected with the clock signal lines are respectively connected with the sub-pixels of different rows. According to a second aspect of the present application, there is provided a display device comprising a display panel as described in any one of the above embodiments. The embodiment of the application provides a display panel and a display device, wherein two scanning lines are arranged between two adjacent rows of sub-pixels in the display panel, two columns of sub-pixels are arranged between two adjacent data lines, the sub-pixels positioned in the same column are connected with the same data line, when the display panel is configured into a first display mode, at least two clock signal lines output effective levels to corresponding scanning lines at the same time, at least two scanning lines connected with the at least two clock signal lines are respectively connected with the sub-pixels of different rows, so that the effect of simultaneously starting the sub-pixels of different rows is achieved, and the display panel adopting a DLS strip architecture achieves the effect of a DLG mode. Additional features and advantages of the application will be set forth in the detailed description which follows. Drawings In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the description of the embodiments will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the application and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art. For a more complete understanding of the present application and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts throughout the following description. Fig. 1 is a schematic diagram showing a target display effect when DLG timing is adopted, and a display effect when DLG timing is adopted for a comparative display device adopting a 1G1D pixel architecture. Fig. 1 (a) is a schematic diagram of a target display effect when the DLG timing is adopted, and fig. 1 (b) is a schematic diagram of a display effect when the DLG timing is adopted for a comparative display device adopting a 1G1D pixel architecture. Fig. 2 is a schematic diagram showing the display effect of a comparative display device using DLG timing and DLS strip architecture. Fig. 3 is a schematic plan view of a display panel according to an embodiment of the application. Fig. 4