CN-122024619-A - Driving circuit, driving method thereof and display panel

CN122024619ACN 122024619 ACN122024619 ACN 122024619ACN-122024619-A

Abstract

The application provides a driving circuit and a driving method thereof, and a display panel, wherein the driving circuit comprises a plurality of shift registers, a plurality of first control sub-circuits and a plurality of second control sub-circuits, the nth first control sub-circuits are respectively and electrically connected with enable signal lines, first grid control signal lines, second grid control signal lines and starting signal input ends of the nth shift registers and are configured to drive the nth shift registers to start scanning or stop scanning, and the nth second control sub-circuits are respectively and electrically connected with the second grid control signal lines, reset signal input ends of the nth shift registers and signal output ends of the (n+1) th shift registers and are configured to reset the nth shift registers under the common control of signals output by the (n+1) th shift registers and signals transmitted by the second grid control signal lines. The driving circuit is used for preparing the display panel with the partial refreshing function, and power consumption is reduced.

Inventors

ZHAO JING
LIU YUJIE
JI CHENGWEI
HUANG YIKUN

Assignees

北京京东方显示技术有限公司
京东方科技集团股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260324

Claims (12)

1. A driving circuit, characterized by comprising: the n-th stage of shift register comprises an opening signal input end, a resetting signal input end and a signal output end, and the signal output end is electrically connected with at least one row of sub-pixels; The first control sub-circuits are respectively and electrically connected with the enable signal line, the first grid control signal line, the second grid control signal line and the starting signal input end of the n-th stage shift register, and the n-th first control sub-circuit is configured to drive the n-th stage shift register to start scanning or stop scanning under the common control of a first grid control signal transmitted by the first grid control signal line and a second grid control signal transmitted by the second grid control signal line; The n-th second control sub-circuit is electrically connected with the second grid control signal line, the reset signal input end of the n-th shift register and the signal output end of the n+1th shift register respectively, and is configured to reset the n-th shift register under the common control of the signal output end of the n+1th shift register and the second grid control signal, wherein n is a positive integer.
2. The driver circuit according to claim 1, wherein an inverter is provided between the first gate control signal line and the second gate control signal line, and wherein phases of a first gate control signal transmitted by the first gate control signal line and a second gate control signal transmitted by the second gate control signal line are opposite.
3. The drive circuit of claim 2, wherein the first control sub-circuit comprises a trigger transistor and an auxiliary transistor; in any one of the first control subcircuits, a first pole of the trigger transistor is electrically connected with the enabling signal line, a second pole of the trigger transistor is electrically connected with an opening signal input end of the shift register, and a second pole of the auxiliary transistor is electrically connected with the opening signal input end of the shift register.
4. The driving circuit according to claim 3, wherein, In the case of n=1, the gate of the trigger transistor is electrically connected to the first gate control signal line, the first pole of the auxiliary transistor is electrically connected to the first power supply signal line, and the gate of the auxiliary transistor is electrically connected to the second gate control signal line; n >1, the gate of the trigger transistor is electrically connected to the second gate control signal line, the first electrode of the auxiliary transistor is electrically connected to the signal output terminal of the shift register of the previous stage, and the gate of the auxiliary transistor is electrically connected to the first gate control signal line.
5. The drive circuit of claim 4, wherein the second control subcircuit comprises an exclusive or gate comprising a first input, a second input, and an output; the first input end of the exclusive-or gate is electrically connected with the second grid control signal line, the second input end of the exclusive-or gate is electrically connected with the signal output end of the shift register of the next stage, and the output end of the exclusive-or gate is electrically connected with the reset signal input end of the shift register of the previous stage.
6. The driving circuit according to claim 5, wherein the number of the first control sub-circuits is the same as the number of the shift registers, and the number of the second control sub-circuits is smaller than or equal to the number of the shift registers.
7. The drive circuit according to claim 6, wherein in a first display mode, the enable signal line is configured to transmit an enable signal to a1 st one of the plurality of first control sub-circuits; A first gate control signal transmitted by the first gate control signal line is configured to control the trigger transistor in the 1st one of the first control sub-circuits to be turned on, and a second gate control signal transmitted by the second gate control signal line is configured to control the auxiliary transistor in the 1st one of the first control sub-circuits to be turned off; A second gate control signal transmitted by the second gate control signal line is configured to control the trigger transistor in the 2 nd to nth first control sub-circuits to be turned off, and a first gate control signal transmitted by the first gate control signal line is configured to control the auxiliary transistor in the 2 nd to nth first control sub-circuits to be turned on; the 1 st to nth shift registers are configured to scan line by line.
8. The driving circuit of claim 6, wherein, in the second display mode, In a first stage, a first gate control signal transmitted by the first gate control signal line is configured to control the trigger transistor in the 1 st one of the first control sub-circuits to be turned on and also control the auxiliary transistors in the 2 nd to m-1 st one of the first control sub-circuits to be turned on; the second gate control signal transmitted by the second gate control signal line is configured to control the auxiliary transistor in the 1 st one of the first control sub-circuits to be turned off and also control the trigger transistor in the 2 nd to m-1 st one of the first control sub-circuits to be turned off; In a second stage, the enable signal line is configured to transmit an enable signal to an mth one of the first control sub-circuits, a second gate control signal transmitted by the second gate control signal line is configured to control the trigger transistor in the mth one of the first control sub-circuits to be turned on, and a first gate control signal transmitted by the first gate control signal line is configured to control the auxiliary transistor in the mth one of the first control sub-circuits to be turned off; In a third stage, a second gate control signal transmitted by the second gate control signal line is configured to control the trigger transistor in the m+1th to nth first control sub-circuits to be turned off, and a first gate control signal transmitted by the first gate control signal line is configured to control the auxiliary transistor in the m+1th to nth first control sub-circuits to be turned on; The m-th shift register in the plurality of shift registers is a starting scanning line, m is a positive integer, and m+1 is smaller than n.
9. The drive circuit of claim 7, wherein in the second phase, the enable signal and the first gate control signal are in opposite phases.
10. The driving circuit according to any one of claims 6 to 8, wherein in a third display mode, a second gate control signal transmitted by the second gate control signal line is configured to control the trigger transistor in the n+1th of the first control sub-circuits to be turned on, and a first gate control signal transmitted by the first gate control signal line is configured to control the auxiliary transistor in the n+1th of the first control sub-circuits to be turned off; The n+1th shift register in the plurality of shift registers is a stop scan line.
11. A display panel comprising the drive circuit according to any one of claims 1 to 10.
12. A driving method of a driving circuit, applied to drive the driving circuit according to any one of claims 1 to 10, the method comprising: the first gate control signal line transmits a first gate control signal; the second gate control signal line transmits a second gate control signal; the nth first control sub-circuit drives the nth shift register to start scanning or stop scanning according to the first grid control signal and the second grid control signal; And the nth second control sub-circuit resets the nth shift register according to the signal output by the signal output end of the (n+1) th shift register and the second grid control signal.

Description

Driving circuit, driving method thereof and display panel Technical Field The present application relates to the field of display technologies, and in particular, to a driving circuit, a driving method thereof, and a display panel. Background With the rapid development of display technology, users have increased many new demands for audio and video displays, and in some display products, there is a need for partially refreshing the display. Currently, local refreshing display is mostly realized by designing a local area refreshing display new picture and a local area display black picture. However, the partial region display black screen is still substantially full-face refresh, only the partial region display black screen is not truly partial refresh, and the power consumption of this scheme is large. Disclosure of Invention The application provides a driving circuit, a driving method thereof and a display panel, and aims to solve the problems. The embodiment of the application adopts the following technical scheme: in a first aspect, the present application provides a driving circuit comprising: the n-th stage of shift register comprises an opening signal input end, a resetting signal input end and a signal output end, and the signal output end is electrically connected with at least one row of sub-pixels; The first control sub-circuits are respectively and electrically connected with the enable signal line, the first grid control signal line, the second grid control signal line and the starting signal input end of the n-th stage shift register, and the n-th first control sub-circuit is configured to drive the n-th stage shift register to start scanning or stop scanning under the common control of a first grid control signal transmitted by the first grid control signal line and a second grid control signal transmitted by the second grid control signal line; The n-th second control sub-circuit in the plurality of second control sub-circuits is electrically connected with the second grid control signal line, the reset signal input end of the n-th shift register and the signal output end of the n+1th shift register respectively and is configured to reset the n-th shift register under the common control of the signal output by the signal output end of the n+1th shift register and the second grid control signal, wherein n is a positive integer. In some driving circuits provided by the embodiments of the present application, an inverter is disposed between the first gate control signal line and the second gate control signal line, and phases of a first gate control signal transmitted by the first gate control signal line and a second gate control signal transmitted by the second gate control signal line are opposite. In some driving circuits provided by embodiments of the present application, the first control sub-circuit includes a trigger transistor and an auxiliary transistor; in any one of the first control subcircuits, a first pole of the trigger transistor is electrically connected with the enabling signal line, a second pole of the trigger transistor is electrically connected with an opening signal input end of the shift register, and a second pole of the auxiliary transistor is electrically connected with the opening signal input end of the shift register. In some of the drive circuits provided by embodiments of the present application, In the case of n=1, the gate of the trigger transistor is electrically connected to the first gate control signal line, the first pole of the auxiliary transistor is electrically connected to the first power supply signal line, and the gate of the auxiliary transistor is electrically connected to the second gate control signal line; n >1, the gate of the trigger transistor is electrically connected to the second gate control signal line, the first electrode of the auxiliary transistor is electrically connected to the signal output terminal of the shift register of the previous stage, and the gate of the auxiliary transistor is electrically connected to the first gate control signal line. In some driving circuits provided by embodiments of the present application, the second control sub-circuit includes an exclusive or gate, the exclusive or gate including a first input terminal, a second input terminal, and an output terminal; the first input end of the exclusive-or gate is electrically connected with the second grid control signal line, the second input end of the exclusive-or gate is electrically connected with the signal output end of the shift register of the next stage, and the output end of the exclusive-or gate is electrically connected with the reset signal input end of the shift register of the previous stage. In some driving circuits provided by the embodiments of the present application, the number of the first control sub-circuits is the same as the number of the shift registers, and the number of the second control sub-circuits is less than or equal to the n