CN-122024620-A - Shift register and display panel

CN122024620ACN 122024620 ACN122024620 ACN 122024620ACN-122024620-A

Abstract

The embodiment of the invention discloses a shift register and a display panel, wherein the shift register comprises an input module, a first output module and a second output module, wherein the input end of the input module is connected with an input signal, the input module is used for transmitting the input signal to a first node, the first output module is used for generating a first grid driving signal according to the voltage of the first node and outputting the first grid driving signal from the first output end of the first output module, the voltage of the first node is latched when the input module is turned off, the first control end of the second output module and the first output end of the first output module are connected to a second node, the second control end of the second output module and the second output end of the first output module are connected to a third node, the second output module is used for generating and outputting a second grid driving signal according to the voltage of the second node and the third node, and the short pulse width level of the first grid driving signal is opposite to the short pulse width level of the second grid driving signal. The frame of the display panel is compressed, and the narrow frame design is realized.

Inventors

GUO ENQING
GAI CUILI
GUO SHUANG
JIN XIAOYANG

Assignees

云谷（固安）科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260326

Claims (10)

1. The shift register is characterized by comprising an input module, a first output module and a second output module; The input end of the input module is connected with an input signal, the output end of the input module and the control end of the first output module are connected to a first node, and the input module is used for transmitting the input signal to the first node; The first output module is used for generating a first grid driving signal according to the voltage of the first node and outputting the first grid driving signal from a first output end of the first output module, and latching the voltage of the first node when the input module is turned off; The first control end of the second output module and the first output end of the first output module are connected to a second node, the second control end of the second output module and the second output end of the first output module are connected to a third node, and the second output module is used for generating and outputting a second grid driving signal according to the voltage of the second node and the voltage of the third node; Wherein the short pulse width level of the first gate driving signal is opposite to the short pulse width level of the second gate driving signal.
2. The shift register according to claim 1, wherein the first output module comprises a first inverting unit and a second inverting unit, a first input terminal of the first inverting unit is connected to a first voltage signal, a second input terminal of the first inverting unit is connected to a second voltage signal, a control terminal of the first inverting unit is connected to the first node, and an output terminal of the first inverting unit is connected to the second node; The first input end of the second inverting unit is connected with the first voltage signal, the second input end of the second inverting unit is connected with the second voltage signal, the control end of the second inverting unit is connected with the second node, the output end of the second inverting unit is connected with the third node, and the third node is connected with the first node; Preferably, the first inverting unit includes a first transistor and a second transistor, the second inverting unit includes a third transistor and a fourth transistor, the gate of the first transistor and the gate of the second transistor are both connected to the first node, the first pole of the first transistor and the first pole of the third transistor are both connected to the first voltage signal, the second pole of the first transistor and the first pole of the second transistor are connected to a fourth node, the fourth node is connected to the second node, the second pole of the second transistor and the second pole of the fourth transistor are both connected to the second voltage signal, the second pole of the third transistor and the first pole of the fourth transistor are both connected to the third node, the first node is connected to the third node, and the gate of the third transistor and the gate of the fourth transistor are both connected to the second node; preferably, the short pulse width level of the input signal is the same as the short pulse width level of the second gate driving signal.
3. The shift register according to claim 1, wherein the first output module comprises a first inverting unit, a second inverting unit and a switching unit, a first input end of the first inverting unit is connected to a first voltage signal, a second input end of the first inverting unit is connected to a second voltage signal, a control end of the first inverting unit is connected to the first node, and an output end of the first inverting unit is connected to the third node; The input end of the switch unit is connected with the first node, the output end of the switch unit is connected with the second node, and the switch unit is used for cutting off the connection path between the second node and the first node when the input module is conducted; the first input end of the second inverting unit is connected with the first voltage signal, the second input end of the second inverting unit is connected with the second voltage signal, the control end of the second inverting unit is connected with the third node, and the output end of the second inverting unit is connected with the second node; preferably, the short pulse width level of the input signal is the same as the short pulse width level of the first gate driving signal.
4. A shift register as claimed in claim 3, characterized in that the first inverting unit comprises a first transistor and a second transistor, the second inverting unit comprises a third transistor and a fourth transistor, the switching unit comprises a fifth transistor, the gate of the first transistor and the gate of the second transistor are both connected to the first node, the first pole of the first transistor is connected to the first voltage signal, the second pole of the first transistor and the first pole of the second transistor are connected to a fourth node, the second pole of the second transistor is connected to the second voltage signal, and the fourth node is connected to the third node; The grid electrode of the third transistor and the grid electrode of the fourth transistor are both connected with the third node, the first electrode of the third transistor is connected with the first voltage signal, the second electrode of the third transistor and the first electrode of the fourth transistor are connected with the second node, and the second electrode of the fourth transistor is connected with the second voltage signal; a first electrode of the fifth transistor is connected with the first node, a second electrode of the fifth transistor is connected with the second node, and a grid electrode of the fifth transistor is connected with a first clock signal; Preferably, the switching unit further includes a sixth transistor, a gate of the sixth transistor is connected to the second clock signal, a first pole of the sixth transistor is connected to the first node, and a second pole of the sixth transistor is connected to the second node; Preferably, a channel type of the sixth transistor is different from a channel type of the fifth transistor; preferably, the fifth transistor is a P-type transistor, and the sixth transistor is an N-type transistor; preferably, the phase difference between the first clock signal and the second clock signal is 180 °.
5. The shift register according to claim 1, wherein the second output module comprises a first output unit and a second output unit, a control end of the first output unit is connected to the second node, a control end of the second output unit is connected to the third node, an input end of the first output unit is connected to a first voltage signal, an output end of the first output unit and an output end of the second output unit are connected to a fifth node, the fifth node is used for outputting the second gate driving signal, and an input end of the second output unit is connected to a third clock signal; Preferably, the first output unit includes a seventh transistor, the second output unit includes an eighth transistor, a gate of the seventh transistor is connected to the second node, a first pole of the seventh transistor is connected to the first voltage signal, a second pole of the seventh transistor is connected to the fifth node, a gate of the eighth transistor is connected to the third node, a first pole of the eighth transistor is connected to the third clock signal, and a second pole of the eighth transistor is connected to the fifth node; preferably, the channel type of the seventh transistor is the same as the channel type of the eighth transistor; preferably, the seventh transistor and the eighth transistor are P-type transistors.
6. The shift register of claim 5, wherein the second output module further comprises a memory cell, a first end of the memory cell being connected to the fifth node, a second end of the memory cell being connected to a control end of the second output cell; preferably, the storage unit includes a storage capacitor, a first end of the storage capacitor is connected to the fifth node, and a second end of the storage capacitor is connected to the control end of the second output unit.
7. The shift register according to claim 5, wherein the second output module further comprises an auxiliary unit, the auxiliary unit is connected in series to a connection path between the control end of the second output unit and the third node, the control end of the auxiliary unit is connected to a voltage control signal, and the auxiliary unit is configured to prevent the voltage of the control end of the second output unit from being transmitted to the third node; preferably, the auxiliary unit includes a ninth transistor, a first pole of the ninth transistor is connected to the third node, a second pole of the ninth transistor is connected to the control terminal of the second output unit, and a gate of the ninth transistor is connected to the voltage control signal.
8. The shift register of claim 1, wherein the input module comprises a tenth transistor having a gate coupled to the second clock signal, a first pole coupled to the input signal, and a second pole coupled to the first node; Preferably, the input module further comprises an eleventh transistor, a gate of the eleventh transistor is connected to the first clock signal, a first pole of the eleventh transistor is connected to the input signal, and a second pole of the eleventh transistor is connected to the first node; Preferably, a channel type of the tenth transistor is different from a channel type of the eleventh transistor; Preferably, the tenth transistor is a P-type transistor, and the eleventh transistor is an N-type transistor; preferably, the phase difference between the first clock signal and the second clock signal is 180 °.
9. A display panel comprising a gate driving circuit, wherein the gate driving circuit comprises a plurality of shift registers according to any one of claims 1 to 8, a plurality of the shift registers are cascaded, and the input signal to which the shift register of the next stage is connected is provided by a first output terminal of the first output module or an output terminal of the second output module of the shift register of the present stage, among the plurality of cascaded shift registers, wherein the input signal of the shift register of the first stage is provided by a trigger signal line.
10. The display panel according to claim 9, wherein the shift register includes an input terminal, a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a first output terminal, and a second output terminal, and the input terminal of the shift register of the next stage is connected to the first output terminal of the shift register of the present stage or the second output terminal of the shift register of the present stage; The input end of the input module is used as the input end of the shift register, the first output end of the first output module is used as the first output end of the shift register, the output end of the second output module is used as the second output end of the shift register, the second control end of the input module is used as the first clock signal end of the shift register, the first control end of the input module is used as the second clock signal end of the shift register, and the second input end of the second output module is used as the third clock signal end of the shift register; The display panel further comprises a first clock signal line, a second clock signal line, a third clock signal line and a fourth clock signal line, wherein the first clock signal end of the shift register of the odd-numbered stage is connected with the first clock signal line, and the first clock signal end of the shift register of the even-numbered stage is connected with the fourth clock signal line; the second clock signal ends of the shift registers of the odd-numbered stages are connected with the second clock signal line, and the second clock signal ends of the shift registers of the even-numbered stages are connected with the third clock signal line; the third clock signal ends of the shift registers of the odd-numbered stages are connected with the third clock signal line, and the first clock signal ends of the shift registers of the even-numbered stages are connected with the first clock signal line; Preferably, the phase difference between the first clock signal transmitted on the first clock signal line and the second clock signal transmitted on the second clock signal line is 180 °; preferably, the phase difference between the third clock signal transmitted on the third clock signal line and the fourth clock signal transmitted on the fourth clock signal line is 180 °.

Description

Shift register and display panel Technical Field The embodiment of the invention relates to the technical field of display, in particular to a shift register and a display panel. Background With the development of display technology, the requirements of users on the display effect of the display panel are increasing. The display panel generally includes a shift register for providing gate driving signals to each stage of pixel circuits, and the existing shift register is complex and is not beneficial to realizing a narrow frame. Disclosure of Invention The embodiment of the invention provides a shift register and a display panel, which are used for reducing the complexity of the shift register and reducing the frame of the display panel. According to an aspect of the present invention, there is provided a shift register including an input module, a first output module, and a second output module; The input end of the input module is connected with an input signal, the output end of the input module and the control end of the first output module are connected to a first node, and the input module is used for transmitting the input signal to the first node; The first output module is used for generating a first grid driving signal according to the voltage of the first node and outputting the first grid driving signal from a first output end of the first output module, and latching the voltage of the first node when the input module is turned off; The first control end of the second output module and the first output end of the first output module are connected to a second node, the second control end of the second output module and the second output end of the first output module are connected to a third node, and the second output module is used for generating and outputting a second grid driving signal according to the voltage of the second node and the voltage of the third node; Wherein the short pulse width level of the first gate driving signal is opposite to the short pulse width level of the second gate driving signal. Optionally, the first output module includes a first inverting unit and a second inverting unit, a first input end of the first inverting unit is connected to a first voltage signal, a second input end of the first inverting unit is connected to a second voltage signal, a control end of the first inverting unit is connected to the first node, and an output end of the first inverting unit is connected to the second node; The first input end of the second inverting unit is connected with the first voltage signal, the second input end of the second inverting unit is connected with the second voltage signal, the control end of the second inverting unit is connected with the second node, the output end of the second inverting unit is connected with the third node, and the third node is connected with the first node; Optionally, the first inverting unit includes a first transistor and a second transistor, the second inverting unit includes a third transistor and a fourth transistor, the gate of the first transistor and the gate of the second transistor are both connected to the first node, the first pole of the first transistor and the first pole of the third transistor are both connected to the first voltage signal, the second pole of the first transistor and the first pole of the second transistor are connected to a fourth node, the fourth node is connected to the second node, the second pole of the second transistor and the second pole of the fourth transistor are both connected to the second voltage signal, the second pole of the third transistor and the first pole of the fourth transistor are both connected to the third node, the first node is connected to the third node, and the gate of the third transistor and the gate of the fourth transistor are both connected to the second node; optionally, the short pulse width level of the input signal is the same as the short pulse width level of the second gate driving signal. Optionally, the first output module includes a first inverting unit, a second inverting unit and a switch unit, a first input end of the first inverting unit is connected to a first voltage signal, a second input end of the first inverting unit is connected to a second voltage signal, a control end of the first inverting unit is connected to the first node, and an output end of the first inverting unit is connected to the third node; The input end of the switch unit is connected with the first node, the output end of the switch unit is connected with the second node, and the switch unit is used for cutting off the connection path between the second node and the first node when the input module is conducted; the first input end of the second inverting unit is connected with the first voltage signal, the second input end of the second inverting unit is connected with the second voltage signal, the control end of the second inverting unit is connected with the third node, and