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CN-122024622-A - Display device and driving method thereof

CN122024622ACN 122024622 ACN122024622 ACN 122024622ACN-122024622-A

Abstract

The application provides a display device and a driving method thereof. In an i-th stage gate driving unit of the display device, a gate of the first transistor is electrically connected to the second node, a source and a drain of the first transistor are electrically connected to the first clock signal line and the gate driving signal output terminal, respectively, a gate of the second transistor is electrically connected to the first frequency division signal input terminal, a source and a drain of the second transistor are electrically connected to the second node and the first node, respectively, a gate and a source of the third transistor are both electrically connected to the second frequency division signal input terminal, a gate of the fourth transistor is electrically connected to a drain of the third transistor, a source and a drain of the fourth transistor are electrically connected to the first power line and the second node, respectively, a gate of the fifth transistor is electrically connected to the first frequency division signal input terminal, and a source and a drain of the fifth transistor are electrically connected to the first power line and the drain of the third transistor, respectively. By controlling the level states of the first frequency division signal input end and the second frequency division signal input end, different areas of the display panel are refreshed by adopting different refresh frequencies, and the power consumption of the display device is reduced.

Inventors

  • LI HAO

Assignees

  • 广州华星光电半导体显示技术有限公司

Dates

Publication Date
20260512
Application Date
20260330
Priority Date
20260121

Claims (13)

  1. 1. A display device, the display device comprising a display panel, the display panel comprising at least one gate driving circuit and a plurality of pixel units, the gate driving circuit comprising N-stage cascade gate driving units, N being a positive integer, N-stage an i-th stage of the gate driving units comprising: A first transistor having a gate electrically connected to the second node, one of a source and a drain electrically connected to the first clock signal line, and the other of the source and the drain electrically connected to the gate driving signal output terminal; A second transistor having a gate electrically connected to the first divided signal input terminal, one of a source and a drain electrically connected to the second node, and the other of the source and the drain electrically connected to the first node; A third transistor having a gate, a source and a drain electrically connected to the second divided signal input terminal; A fourth transistor having a gate electrically connected to the other of the source and the drain of the third transistor, one of the source and the drain electrically connected to the first power line, the other of the source and the drain electrically connected to the second node, and And a fifth transistor having a gate electrically connected to the first frequency-divided signal input terminal, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to the other of the source and the drain of the third transistor.
  2. 2. The display device according to claim 1, wherein a display area of the display panel includes a first region and a second region arranged in a column direction of the plurality of pixel units, a plurality of rows of the pixel units in the first region are electrically connected to a1 st-stage gate driving unit, a plurality of rows of the pixel units in the second region are electrically connected to a j-th-stage gate driving unit, j and k are positive integers, and 1< j < k is equal to or less than N; the refresh frequency of the second area is higher than the refresh frequency of the first area; In the driving period of the P-th frame picture, the second frequency division signal input end inputs a second level signal, the first frequency division signal input end inputs a first level signal, the 1 st stage gate driving unit to the N-th stage gate driving unit sequentially output a gate driving signal of the first level, and P is a positive integer; In a first time period in the driving period of the P+1st frame picture, the second frequency division signal input end inputs a first level signal, the first frequency division signal input end inputs a second level signal, and the 1 st stage gate driving unit outputs a second level gate driving signal to the j-1 st stage gate driving unit; In a second period of the driving period of the p+1st frame of picture, the second frequency division signal input end inputs a second level signal, the first frequency division signal input end inputs a first level signal, and the j-th stage gate driving unit to the k-th stage gate driving unit sequentially output gate driving signals of the first level.
  3. 3. The display device according to claim 2, wherein k < N, the display region further includes a third region arranged along the column direction with the first region, the second region, and a plurality of rows of the pixel units in the third region are electrically connected with the (k+1) -th-stage gate driving unit to the (N) -th-stage gate driving unit; The refresh frequency of the first area and the refresh frequency of the third area are the same; The driving period of the p+1st frame of picture further includes a third period, in which the first level signal is input to the second frequency-division signal input terminal, the second level signal is input to the first frequency-division signal input terminal, and the k+1st stage gate driving unit outputs the gate driving signal of the second level to the nth stage gate driving unit.
  4. 4. The display device according to claim 1, wherein when the first frequency-divided signal input terminal inputs a first level signal and the second frequency-divided signal input terminal inputs a second level signal, the second transistor and the fifth transistor are turned on, the third transistor and the fourth transistor are turned off, and a potential of the first node is transmitted to the second node.
  5. 5. The display device according to claim 1, wherein when a second level signal is input to the first divided signal input terminal and a first level signal is input to the second divided signal input terminal, the second transistor and the fifth transistor are turned off, the third transistor and the fourth transistor are turned on, and a potential of the second node is pulled down to a potential of the first power supply line.
  6. 6. The display device according to claim 1, wherein signals input to the first divided signal input terminal and the second divided signal input terminal are inverted.
  7. 7. The display device according to claim 1, wherein the gate driving unit of the i-th stage further comprises: A sixth transistor having a gate, one of a source and a drain electrically connected to the start signal input terminal, and the other of the source and the drain electrically connected to the first node; A seventh transistor having a gate electrically connected to the first node, one of a source and a drain electrically connected to the first clock signal line, and the other of the source and the drain electrically connected to a stage signal output terminal; An eighth transistor having a gate electrically connected to the reset signal input terminal, one of a source and a drain electrically connected to the first node, and the other of the source and the drain electrically connected to the first power line; A ninth transistor having a gate electrically connected to the start signal input terminal, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to a third node; A tenth transistor having a gate, one of a source and a drain electrically connected to the first control signal input terminal, and the other of the source and the drain electrically connected to the third node; An eleventh transistor having a gate electrically connected to the first node, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to the third node; A twelfth transistor having a gate electrically connected to the third node, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to the first node; a thirteenth transistor having a gate electrically connected to the third node, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to the stage signal output terminal; a fourteenth transistor having a gate electrically connected to the third node, one of a source and a drain electrically connected to the first power line or the second power line, and the other of the source and the drain electrically connected to the gate driving signal output terminal; A fifteenth transistor having a gate electrically connected to the start signal input terminal, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to a fourth node; a sixteenth transistor having a gate, one of a source and a drain electrically connected to the second control signal input terminal, and the other of the source and the drain electrically connected to the fourth node; a seventeenth transistor having a gate electrically connected to the first node, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to the fourth node; An eighteenth transistor having a gate electrically connected to the fourth node, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to the first node; A nineteenth transistor having a gate electrically connected to the fourth node, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to the stage signal output terminal; a twentieth transistor having a gate electrically connected to the fourth node, one of a source and a drain electrically connected to the first power line or the second power line, and the other of the source and the drain electrically connected to the gate driving signal output terminal; A twenty-first transistor having a gate electrically connected to a first pull-down control signal terminal, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to the first node; a first capacitor having two plates electrically connected to the first node and the stage signal output terminal, respectively, and And the second capacitor, the bipolar plate is electrically connected to the second node and the grid driving signal output end respectively.
  8. 8. The display device according to claim 7, wherein the gate driving unit of the i-th stage further comprises: and a twenty-second transistor having a gate electrically connected to the second pull-down control signal terminal, one of a source and a drain electrically connected to the first power line, and the other of the source and the drain electrically connected to the gate driving signal output terminal.
  9. 9. A driving method of a display device, the display device comprising a display panel including a plurality of pixel units and N-stage cascade gate driving units, a display region of the display panel including a first region and a second region arranged in a column direction of the plurality of pixel units, a plurality of rows of the pixel units in the first region being electrically connected with the 1 st stage gate driving unit to the j-1 st stage gate driving unit, a plurality of rows of the pixel units in the second region being electrically connected with the j-th stage gate driving unit to the k-th stage gate driving unit, j and k being positive integers, and 1< j < k being N, a refresh frequency of the second region being higher than a refresh frequency of the first region, the driving method comprising: In the driving period of the P-th frame picture, a second level signal is input to the second frequency division signal input end of the gate driving unit, a first level signal is input to the first frequency division signal input end of the gate driving unit, and the 1 st-stage gate driving unit to the N-stage gate driving unit sequentially output gate driving signals of the first level, wherein P is a positive integer; In a first time period in the driving period of the P+1st frame picture, a first level signal is input to a second frequency division signal input end of the gate driving unit, and a second level signal is input to a first frequency division signal input end of the gate driving unit, so that the 1 st stage gate driving unit to the j-1 st stage gate driving unit output a second level gate driving signal; in a second period of the driving period of the p+1st frame of picture, a second frequency division signal input end of the gate driving unit inputs a second level signal, and a first frequency division signal input end of the gate driving unit inputs a first level signal, so that the j-th stage gate driving unit to the k-th stage gate driving unit sequentially output gate driving signals of the first level.
  10. 10. The driving method according to claim 9, wherein k < N, the display region of the display panel further includes a third region arranged along the column direction with the first region, the second region, and a plurality of rows of the pixel cells in the third region are electrically connected with the (k+1) -th-stage gate driving unit to the (N) -th-stage gate driving unit; The refresh frequency of the first area and the refresh frequency of the third area are the same; The driving period of the p+1st frame picture further includes a third period, and the driving method further includes: And in the third time period, the first level signal is input to the second frequency division signal input end of the gate driving unit, and the second level signal is input to the first frequency division signal input end of the gate driving unit, so that the (k+1) th stage gate driving unit to the (N) th stage gate driving unit output the gate driving signal of the second level.
  11. 11. The driving method according to claim 9, wherein when the first frequency-divided signal input terminal inputs a first level signal and the second frequency-divided signal input terminal inputs a second level signal, the second transistor and the fifth transistor in the gate driving unit are turned on, the third transistor in the gate driving unit is turned off, and a potential of the first node of the gate driving unit is transmitted to the second node of the gate driving unit.
  12. 12. The driving method according to claim 9, wherein when the second level signal is input to the first divided signal input terminal and the first level signal is input to the second divided signal input terminal, the second transistor and the fifth transistor in the gate driving unit are turned off, the third transistor and the fourth transistor in the gate driving unit are turned on, and a potential of the second node of the gate driving unit is pulled down to a potential of the first power supply line.
  13. 13. The driving method according to claim 9, wherein signals input to the first divided signal input terminal and the second divided signal input terminal are inverted.

Description

Display device and driving method thereof The present application claims priority from chinese patent application No. 202610091515.X filed on 21, 01, 2026, which is incorporated herein by reference. Technical Field The application relates to the technical field of display, in particular to a display device and a driving method thereof. Background In practical applications, different areas of a display panel of a display device often need to present different display contents. For example, in some application scenarios, a partial region of the display panel needs to display dynamically changing content, while other regions need only display static content or slower changing content. In a conventional display device, a gate driving circuit of a display panel generally drives an entire display area with a uniform refresh frequency. Specifically, the gate driving circuit includes a plurality of cascade-connected gate driving units, which sequentially output gate driving signals according to a fixed timing sequence to drive the pixel units in the display panel to display. In this driving mode, all regions of the display panel are refreshed at the same refresh frequency, regardless of whether or not the contents displayed in the respective regions need to be frequently updated. When certain areas of the display panel display static content or content that changes more slowly, unnecessary power consumption increases if these areas are still refreshed at a higher refresh frequency. This is because the gate driving unit needs to output a gate driving signal to turn on a transistor in the pixel unit in each refresh period, thereby charging the pixel unit. For areas where static content is displayed, frequent refresh operations do not change the display content, but continue to consume power. Particularly in a large-sized display panel or a high-resolution display panel, the uniform use of a high refresh frequency to drive the entire display area results in higher overall power consumption of the display device due to the larger number of pixel units. Therefore, a new solution is needed to solve the above-mentioned problems. Disclosure of Invention The application aims to provide a display device and a driving method thereof, aiming to reduce the power consumption of the display device. The application provides a display device, which comprises a display panel, wherein the display panel comprises at least one grid driving circuit and a plurality of pixel units, the grid driving circuit comprises N-stage cascaded grid driving units, N is a positive integer, the ith stage of the grid driving units in the N-stage grid driving units comprises a first transistor, a grid electrode is electrically connected to a second node, one of the source electrode and the drain electrode is electrically connected to a first clock signal line, the other of the source electrode and the drain electrode is electrically connected to a grid driving signal output end, the second transistor is electrically connected to a first frequency division signal input end, one of the source electrode and the drain electrode is electrically connected to the second node, the other of the source electrode and the drain electrode is electrically connected to a first node, a third transistor is electrically connected to one of the source electrode and the drain electrode in the N-stage grid driving units, the grid electrode is electrically connected to a second frequency division signal input end, the fourth transistor is electrically connected to the other of the source electrode and the drain electrode in the third transistor, one of the source electrode and the drain electrode in the source electrode is electrically connected to a first power line, the other of the source electrode and the drain electrode in the third transistor is electrically connected to the first frequency division signal input end, and the other of the source electrode and the source electrode is electrically connected to the other of the source electrode in the third transistor is connected to the first node. In the display device, a display area of the display panel comprises a first area and a second area which are arranged along the column direction of a plurality of pixel units, a plurality of rows of the pixel units in the first area are electrically connected with a 1 st-stage grid driving unit to a j-1 th stage grid driving unit, a plurality of rows of the pixel units in the second area are electrically connected with the j-th stage grid driving unit to a k-stage grid driving unit, j and k are positive integers, 1< j < k is less than or equal to N, the refresh frequency of the second area is higher than the refresh frequency of the first area, a second level signal is input by a second frequency dividing signal input end in the driving period of a P-th frame picture, a first level signal is input by the first frequency dividing signal input end, a first level driving signal is