CN-122024642-A - Gate driving circuit, driving method thereof, display panel and display device

Abstract

The application discloses a gate driving circuit and a driving method thereof, a display panel and a display device, wherein the gate driving circuit comprises a plurality of cascaded shift registers; the shift register comprises an input module, a conduction control module, an inversion module and an output module, wherein the input module is used for adjusting the potential of a first node based on the potentials of a clock signal end, a third node and an input end, the conduction control module is used for adjusting the potential of the third node based on the potentials of a first voltage signal end, a second voltage signal end, the input end and the first node, the inversion module is used for controlling the potential inversion of the first node and the second node, and the output module is used for enabling the output end to output the voltage of the first voltage signal end or the voltage of a fourth voltage signal end based on the potential of the second node. According to the application, two clock signals are not required to be set to adjust the potential of the first node, so that the number of clock signal lines can be reduced, and the power consumption is reduced.

Inventors

• FENG XUEHUAN
• GAO YANA
• ZHOU XINGYAO

Assignees

• 厦门天马显示科技有限公司

Dates

Publication Date

20260512

Application Date

20260318

Claims (16)

1. 1. The grid driving circuit is characterized by comprising a plurality of cascaded shift registers, a plurality of driving circuits and a plurality of driving circuits, wherein each shift register comprises an input module, a conduction control module, an inversion module and an output module; the input module is respectively and electrically connected with an input end, a clock signal end, a first node and a third node, and is used for adjusting the potential of the first node based on the potentials of the clock signal end, the third node and the input end; The conduction control module is electrically connected with a first voltage signal end, a second voltage signal end, the input end, the first node and the third node respectively, and is used for adjusting the potential of the third node based on the potentials of the first voltage signal end, the second voltage signal end, the input end and the first node; The inverting module is electrically connected with the first node, the second node, the first voltage signal end and the third voltage signal end respectively, and is used for controlling potential inversion of the first node and the second node; The output module is electrically connected with the second node, the first voltage signal end, the fourth voltage signal end and the output end respectively, and the output module is used for enabling the output end to output the voltage of the first voltage signal end or the fourth voltage signal end based on the potential of the second node.
2. 2. The gate driving circuit of claim 1, wherein the second voltage signal terminal, the third voltage signal terminal, and the fourth voltage signal terminal are the same signal terminal.
3. 3. The gate drive circuit of claim 1, wherein the voltage received at the second voltage signal terminal and the third voltage signal terminal is less than the voltage received at the fourth voltage signal terminal.
4. 4. The gate driving circuit according to claim 1, wherein, The output end of the output module of the ith stage is electrically connected with the input end of the (i+1) th stage, and the output end of the output module is also used for being electrically connected with a corresponding pixel driving circuit.
5. 5. The gate drive circuit of claim 1, wherein the output module comprises a first output unit and a second output unit; The first output unit is electrically connected with a fourth first voltage signal end, and the second output unit is electrically connected with a fourth second voltage signal end; The first output unit is used for enabling the output end of the first output unit to output the voltage of the first voltage signal end or the fourth first voltage signal end based on the potential of the second node; The second output unit is used for enabling the output end of the second output unit to output the voltage of the first voltage signal end or the fourth voltage signal end based on the potential of the second node; the output end of the first output unit of the ith stage is electrically connected with the input end of the (i+1) th stage, and the output end of the second output unit is used for being electrically connected with a corresponding pixel driving circuit.
6. 6. The gate drive circuit of claim 5, wherein the first output unit comprises a first output transistor and a second output transistor; the second output unit includes a third output transistor and a fourth output transistor; The grid electrode of the first output transistor, the grid electrode of the second output transistor, the grid electrode of the third output transistor and the grid electrode of the fourth output transistor are all electrically connected with the second node, the second pole of the first output transistor and the first pole of the second output transistor are all electrically connected with the input end of a next-stage shift register, and the second pole of the third output transistor and the first pole of the fourth output transistor are all electrically connected with a corresponding pixel driving circuit; the first pole of the first output transistor and the first pole of the third output transistor are electrically connected with the first voltage signal end, the second pole of the second output transistor is electrically connected with the fourth first voltage signal end, and the second pole of the fourth output transistor is electrically connected with the fourth second voltage signal end; The first output transistor and the third output transistor are first type transistors, and the second output transistor and the fourth output transistor are second type transistors.
7. 7. The gate driving circuit of claim 5, wherein the gate driving circuit comprises a gate driver circuit, The voltage received by the second voltage signal end and the third voltage signal end is smaller than the voltage received by the fourth voltage signal end.
8. 8. The gate driving circuit according to claim 7, wherein, The voltage received by the fourth A voltage signal terminal is smaller than the voltage received by the fourth B voltage signal terminal.
9. 9. The gate drive circuit of claim 1, wherein the input module comprises a first input transistor and a second input transistor; The first electrode of the first input transistor and the first electrode of the second input transistor are electrically connected with the input end, the second electrode of the first input transistor and the second electrode of the second input transistor are connected with the first node, the grid electrode of the first input transistor is connected with the clock signal end, and the grid electrode of the second input transistor is connected with the third node; The second input transistor is a first type transistor, and the first input transistor is a second type transistor.
10. 10. The gate drive circuit of claim 1, wherein the turn-on control module comprises a first transistor, a second transistor, and a third transistor; The first electrode of the first transistor is electrically connected with the first voltage signal end, the second electrode of the first transistor and the first electrode of the second transistor are electrically connected with the third node, the second electrode of the second transistor is electrically connected with the first electrode of the third transistor, and the second electrode of the third transistor is electrically connected with the second voltage signal end; The first transistor is a first type transistor, and the second transistor and the third transistor are second type transistors.
11. 11. The gate drive circuit of claim 1, wherein the inverting module comprises a fourth transistor and a fifth transistor; The grid electrode of the fourth transistor and the grid electrode of the fifth transistor are electrically connected with the first node, the second pole of the fourth transistor and the first pole of the fifth transistor are electrically connected with the second node, the first pole of the fourth transistor is connected with the first voltage signal end, and the second pole of the fifth transistor is connected with the third voltage signal end; wherein the fourth transistor is a first type transistor and the fifth transistor is a second type transistor.
12. 12. The gate drive circuit of claim 1, wherein the output module comprises a fifth output transistor and a sixth output transistor; The grid electrode of the fifth output transistor and the grid electrode of the sixth output transistor are electrically connected with the second node, the second pole of the fifth output transistor and the first pole of the sixth output transistor are electrically connected with the output end, the first pole of the fifth output transistor is electrically connected with the first voltage signal end, and the second pole of the sixth output transistor is electrically connected with the fourth voltage signal end; Wherein the fifth output transistor is a first type transistor and the sixth output transistor is a second type transistor.
13. 13. The gate drive circuit of claim 1, wherein the shift register further comprises a first capacitor, a first end of the first capacitor is electrically connected to the first node, and a second end of the first capacitor is electrically connected to a first level end; the first level end is used for providing a fixed potential.
14. 14. A driving method of a gate driving circuit, characterized by being applied to the gate driving circuit according to any one of claims 1 to 13, the method comprising: in the first stage, the clock signal end is at a second level, the input end is at a first level, the input module enables the first node to be at the second level, the conduction control module enables the third node to be at the first level, the inversion module enables the second node to be at the first level, and the output module enables the output end to be at the second level; In the second stage, the clock signal end is at a first level or a second level, the input end is at the first level, the input module enables the first node to be at the first level, the conduction control module enables the third node to be at the second level, the inversion module enables the second node to be at the second level, and the output module enables the output end to be at the first level; in a third stage, the clock signal end is at a second level, the input end is at the second level, the input module enables the first node to be at a first level, the conduction control module enables the third node to be at the first level, the inversion module enables the second node to be at the second level, and the output module enables the output end to be at the first level; in the fourth stage, the clock signal end is at a first level or a second level, the input end is at a second level, the input module enables the first node to be at the second level, the conduction control module enables the third node to be at the first level, the inversion module enables the second node to be at the first level, and the output module enables the output end to be at the second level; wherein the first level is inverted from the second level.
15. 15. A display panel comprising a pixel driving circuit and a gate driving circuit according to any one of claims 1 to 13.
16. 16. A display device comprising the display panel of claim 15.

Description

Gate driving circuit, driving method thereof, display panel and display device Technical Field The application relates to the field of display, in particular to a gate driving circuit, a driving method thereof, a display panel and a display device. Background With the rapid development of display technology, users have put higher demands on the display effect and performance of the display panel, and thus the display panel is required to be further developed toward low power consumption. In order to achieve low power consumption of the display panel in the related art, a shift register is generally manufactured using a Complementary Metal Oxide Semiconductor (CMOS). However, each stage of the conventional shift register circuit requires two different clock signals, and thus, corresponding clock signal lines are required to be respectively provided for the two clock signals, which results in an increase in the number of clock signal lines and thus higher power consumption. Disclosure of Invention The application provides a grid driving circuit, a driving method thereof, a display panel and a display device, according to the application, two clock signals are not required to be set to adjust the potential of the first node, so that the number of clock signal lines can be reduced, and the power consumption is reduced. In a first aspect, an embodiment of the present application provides a gate driving circuit, including a plurality of shift registers in cascade, where the shift registers include an input module, a conduction control module, an inversion module, and an output module; the input module is respectively and electrically connected with the input end, the clock signal end, the first node and the third node, and is used for adjusting the potential of the first node based on the potentials of the clock signal end, the third node and the input end; the conduction control module is electrically connected with the first voltage signal end, the second voltage signal end, the input end, the first node and the third node respectively and is used for adjusting the potential of the third node based on the potentials of the first voltage signal end, the second voltage signal end, the input end and the first node; the inverting module is electrically connected with the first node, the second node, the first voltage signal end and the third voltage signal end respectively and is used for controlling potential inversion of the first node and the second node; The output module is electrically connected with the second node, the first voltage signal end, the fourth voltage signal end and the output end respectively, and is used for enabling the output end to output the voltage of the first voltage signal end or the fourth voltage signal end based on the potential of the second node. In a second aspect, an embodiment of the present application further provides a driving method of a gate driving circuit, which is applied to the gate driving circuit corresponding to the foregoing embodiment, where the method includes: In the first stage, the clock signal end is the second level, the input end is the first level, the input module enables the first node to be the second level, the conduction control module enables the third node to be the first level, the inversion module enables the second node to be the first level, and the output module enables the output end to be the second level; In the second stage, the clock signal end is a first level or a second level, the input end is the first level, the input module enables the first node to be the first level, the conduction control module enables the third node to be the second level, the inversion module enables the second node to be the second level, and the output module enables the output end to be the first level; in the third stage, the clock signal end is the second level, the input module enables the first node to be the first level, the conduction control module enables the third node to be the first level, the inversion module enables the second node to be the second level, and the output module enables the output end to be the first level; In the fourth stage, the clock signal end is a first level or a second level, the input end is a second level, the input module enables the first node to be the second level, the conduction control module enables the third node to be the first level, the inversion module enables the second node to be the first level, and the output module enables the output end to be the second level; wherein the first level is inverted from the second level. In a third aspect, an embodiment of the present application further provides a display panel, where the display panel includes a pixel driving circuit and a gate driving circuit corresponding to the above embodiment. In a fourth aspect, an embodiment of the present application further provides a display device, where the display device includes a display panel corresponding to the above em