CN-122024654-A - Pixel arrangement

CN122024654ACN 122024654 ACN122024654 ACN 122024654ACN-122024654-A

Abstract

Disclosed is a pixel including a light emitting element connected between a first power supply line and a first node, a first power supply voltage supplied through the first power supply line, a first transistor including a first electrode connected to the first node, a second electrode connected to a second power supply line, the second power supply line being supplied with a second power supply voltage lower than the first power supply voltage, and a second gate electrode supplied with a gate voltage, a first capacitor connected between the second node and a third node, a second transistor connected between a data line to which a data signal is supplied and the third node, and including a gate electrode for receiving a first scan signal, and a second capacitor connected between the second node and the second power supply line. The voltage obtained by subtracting the voltage of the second electrode from the voltage of the second gate electrode has a negative voltage level.

Inventors

JIN XUANJUN
YU YIJING
Pu Jican
Lin Tanyuan
Zhao Zaijiong

Assignees

三星显示有限公司
建国大学校产学协力团

Dates

Publication Date: 20260512
Application Date: 20251103
Priority Date: 20241111

Claims (10)

1. A pixel, the pixel comprising: a light emitting element connected between a first power line through which a first power voltage is supplied and a first node; A first transistor including a first electrode connected to the first node, a second electrode connected to a second power supply line, a first gate electrode connected to the second node, and a second gate electrode supplied with a gate voltage, the second power supply line being supplied with a second power supply voltage lower than the first power supply voltage; A first capacitor connected between the second node and a third node; A second transistor connected between a data line to which a data signal is supplied and the third node and including a gate electrode for receiving the first scan signal, and A second capacitor connected between the second node and the second power line, Wherein a voltage obtained by subtracting the voltage of the second electrode from the voltage of the second gate electrode has a negative voltage level.
2. The pixel according to claim 1, wherein the semiconductor layer of each of the first transistor and the second transistor comprises an oxide semiconductor.
3. The pixel of claim 1, further comprising: And a fourth transistor connected between the first node and the first power line and including a gate electrode receiving a second scan signal.
4. A pixel according to claim 3, further comprising: and a sixth transistor connected between the third node and a ground electrode and including a gate electrode receiving the second scan signal.
5. A pixel according to claim 3, further comprising: and a third transistor connected between the second node and the first transistor and including a gate electrode.
6. The pixel according to claim 5, wherein a third scan signal is provided to the gate electrode of the third transistor.
7. The pixel according to claim 5, wherein the second scan signal is provided to the gate electrode of the third transistor.
8. The pixel of claim 6, further comprising: a fifth transistor connected between the first node and the first transistor and including a gate electrode receiving a transmission signal.
9. The pixel of claim 8, further comprising: A seventh transistor connected between the first node and the second node and including a gate electrode receiving a scan signal obtained by shifting the first scan signal by a predetermined time.
10. The pixel of claim 9, wherein the scan signal and the second scan signal are at active levels during a first period.

Description

Pixel arrangement The present application claims priority from korean patent application No. 10-2024-0158991 filed on 11 months 2024 at 11, the disclosure of which is incorporated herein by reference in its entirety. Technical Field Embodiments of the present disclosure described herein relate to pixels and electronic devices with improved reliability. Background The electronic device may be a device composed of various electronic components such as a display panel displaying an image, an input sensor sensing an external input, and an electronic module. The electronic components may be electrically connected to each other by the signal lines thus differently arranged. The display panel includes a plurality of pixels. Each of the plurality of pixels includes a light emitting element that generates light and a pixel driving circuit that controls an amount of current flowing through the light emitting element. When a leakage current occurs in a pixel driving circuit within a pixel, the amount of current flowing through a light emitting element changes, thereby degrading display quality. Disclosure of Invention Embodiments of the present disclosure provide a pixel and an electronic device with improved reliability. According to an embodiment, a pixel includes a light emitting element connected between a first power supply line and a first node, a first power supply voltage supplied through the first power supply line, a first transistor including a first electrode connected to the first node, a second electrode connected to a second power supply line, the second power supply line being supplied with a second power supply voltage lower than the first power supply voltage, and a second gate electrode supplied with a gate voltage, a first capacitor connected between the second node and a third node, a second transistor connected between a data line to which a data signal is supplied and the third node, and including a gate electrode for receiving a first scan signal, and a second capacitor connected between the second node and the second power supply line. The voltage obtained by subtracting the voltage of the second electrode from the voltage of the second gate electrode has a negative voltage level. The semiconductor layer of each of the first transistor and the second transistor may include an oxide semiconductor. The pixel may further include a fourth transistor connected between the first node and the first power line and including a gate electrode receiving the second scan signal. The pixel may further include a sixth transistor connected between the third node and the ground electrode and including a gate electrode receiving the second scan signal. The pixel may further include a third transistor connected between the second node and the first transistor and including a gate electrode. The third scan signal may be supplied to a gate electrode of the third transistor. The second scan signal may be supplied to a gate electrode of the third transistor. The pixel may further include a fifth transistor connected between the first node and the first transistor and including a gate electrode receiving the emission signal. The pixel may further include a seventh transistor connected between the first node and the second node and including a gate electrode receiving a scan signal obtained by shifting the first scan signal by a predetermined time. During the first period, the scan signal and the second scan signal may be at active levels. Drawings The above and other features of the present disclosure will become apparent by describing in detail embodiments thereof with reference to the accompanying drawings. Fig. 1 is a block diagram of an electronic device according to an embodiment of the present disclosure. Fig. 2 is a perspective view of an electronic device according to an embodiment of the present disclosure. Fig. 3 is a block diagram of an electronic device according to an embodiment of the present disclosure. Fig. 4 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure. Fig. 5 is a timing diagram for describing the operation of an electronic device according to an embodiment of the present disclosure. Fig. 6 is a diagram for describing an operation of a pixel according to an embodiment of the present disclosure. Fig. 7 is a diagram for describing an operation of a pixel according to an embodiment of the present disclosure. Fig. 8A, 8B, and 8C are graphs showing characteristics of transistors according to an embodiment of the present disclosure. Fig. 9 is a diagram for describing an operation of a pixel according to an embodiment of the present disclosure. Fig. 10 is a diagram for describing an operation of a pixel according to an embodiment of the present disclosure. Fig. 11 is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure. Fig. 12 is a timing diagram for describing an operation of an electronic device according to an