CN-122024661-A - Display device

CN122024661ACN 122024661 ACN122024661 ACN 122024661ACN-122024661-A

Abstract

Some embodiments of the present application disclose a display device, the display device includes a power circuit, M driving units, M light emitting units, and M delay circuits, where the first delay circuit and the first driving chip receive a power voltage provided by a first power supply end at the same time, and after a delay period, provide the power voltage to a second driving chip, and because the positions of the second driving chips in the M driving units are different, and/or the delay periods corresponding to the M delay circuits are different, the timings of address trigger signals received by the first driving chips in different driving units are different, and the number of received first instructions is different, so that the corresponding address data determined by each driving chip is different, and the connection structure of the last driving chip and the first driving chip in the next driving unit is not required to be set, so that the difference of address data corresponding to different driving chips can be ensured, and the area and cost of the display device are reduced while the addressing accuracy is ensured.

Inventors

YE YANG
ZHANG CHUNYANG
DONG YUEQI
PANG ZHENHUA
QU CHAOJIE
LI YOUGUI
LIU GUANGXUE
ZHENG YANJIE

Assignees

海信视像科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260204

Claims (10)

1. A display device, comprising: a power circuit including a first power supply terminal configured to provide a power supply voltage and a second power supply terminal configured to provide a backlight power supply voltage; m driving units connected in parallel, wherein M is an integer greater than 1; The first driving unit comprises N driving chips which are connected in series, wherein the first driving unit is any driving unit in the M driving units, and N is an integer greater than or equal to 1; The first light-emitting unit corresponding to the first driving unit comprises N light-emitting subunits, the N light-emitting subunits correspond to the N driving chips, and each light-emitting subunit is configured to emit light under the driving of the corresponding driving chip; the M delay circuits correspond to the M driving units, and a first delay circuit corresponding to the first driving unit is connected with a first driving chip of the first driving unit; The first delay circuit is configured to receive the power supply voltage provided by the first power supply terminal simultaneously with a first driving chip of the first driving unit, and provide the power supply voltage to the first driving chip and a driving chip positioned below the first driving chip after a delay time period; a second driving chip configured to: The second driving chip is the first driving chip or the driving chip positioned below the first driving chip, the positions of the second driving chips for sending the addressing trigger signals in the M driving units are different, and/or the delay time lengths of delay circuits corresponding to the M driving units are different; the first driver chip is configured to: outputting a first instruction to other driving units under the condition that the first driving chip receives the addressing trigger signal; Determining address data corresponding to the first driving chip according to the first number of the acquired first instructions, and sending the address data corresponding to the first driving chip to the next driving chip; The P-th driving chip in the first driving unit is configured to: Receiving address data corresponding to a last driving chip sent by the last driving chip; And determining address data corresponding to the P-th driving chip according to the address data corresponding to the last driving chip, and sending the address data corresponding to the P-th driving chip to the next driving chip until the P-th driving chip is the last driving chip of the first driving unit, wherein P is an integer greater than 1 and less than or equal to N.
2. The display device according to claim 1, wherein the driving chip includes a first data terminal and a second data terminal, the first data terminal of the P-th driving chip of the first driving unit is connected to the second data terminal of the previous driving chip; the second driver chip is further configured to: Transmitting the addressing trigger signal to the previous driving chip through the first data end of the second driving chip; a driver chip located above the second driver chip configured to: receiving an addressing trigger signal of the next driving chip through a second data end of the driving chip positioned above the second driving chip; And sending an addressing trigger signal to the previous driving chip through a first data end of the driving chip positioned above the second driving chip until the driving chip positioned above the second driving chip is the first driving chip of the first driving unit.
3. The display device of claim 1, wherein the driving chip comprises a first data terminal and a second data terminal, the first data terminal of a first driving chip of the first driving unit is connected with the first data terminal of a first driving chip of other driving units; the first driver chip is further configured to: outputting a first instruction to other driving units through a first data end of the first driving chip; Transmitting address data corresponding to the first driving chip to the next driving chip through the second data end of the first driving chip; the P-th driving chip is further configured to: Receiving address data corresponding to a last driving chip sent by the last driving chip through a first data end of the P driving chip; And sending address data corresponding to the P-th driving chip to the next driving chip through the second data end of the P-th driving chip.
4. A display device according to claim 3, further comprising a controller, the controller comprising a third data terminal, the third data terminal being connected to the first data terminal of the first driver chip of the first driver unit; the last driving chip of the first driving unit is configured to: Feeding back a first address completion signal to the first driving chip under the condition that address data corresponding to the last driving chip is determined; the first driver chip is further configured to: outputting a second addressing completion signal through a first data terminal of the first driving chip according to the first addressing completion signal; the controller is configured to: And under the condition that the third data end receives second addressing completion signals respectively sent by the M driving units, outputting a first data packet through the third data end, wherein the first data packet comprises one or more driving data and address data corresponding to a driving chip corresponding to the driving data.
5. The display device of claim 4, wherein the controller is further configured to: The method comprises the steps of respectively outputting second data packets to M driving units, wherein the second data packets comprise address information respectively corresponding to the M driving units, the address information comprises first address data and second address data, the first address data is preset address data of a first driving chip in the driving units, and the second address data is preset address data of a last driving chip in the driving units; After determining the address data corresponding to the first driver chip according to the first number of the acquired first instructions, the first driver chip is further configured to: Acquiring second address data corresponding to the first driving unit from M address information included in the second data packet according to address data corresponding to a first driving chip in the first driving unit; Transmitting address data corresponding to a first driving chip in the first driving unit and second address data corresponding to the first driving unit to a next driving chip; The last driver chip in the first driver unit is further configured to: Under the condition that the address data corresponding to the last driving chip is determined, comparing the address data corresponding to the last driving chip with the second address data corresponding to the first driving unit; If the address data corresponding to the last driving chip is consistent with the second address data corresponding to the first driving unit, feeding back a first address completion signal to the first driving chip; and if the address data corresponding to the last driving chip is inconsistent with the second address data corresponding to the first driving unit, a first address completion signal is not fed back to the first driving chip.
6. The display device of claim 4, wherein the first driver chip of the first driver unit is further configured to: Determining a second number of received second addressing completion signals in case the first addressing completion signal is received; Outputting a second addressing completion signal through the first data terminal of the first driving chip if the second number is identical to the first number; And if the second quantity is inconsistent with the first quantity, waiting until the second quantity is consistent with the first quantity.
7. The display device of any one of claims 4 to 6, wherein the controller is further configured to: If the number of the second addressing completion instructions received through the third data end does not reach M within the first preset duration, controlling the power supply circuit to stop outputting the power supply voltage through the first power supply end, and controlling the power supply circuit to provide the power supply voltage again through the first power supply end after the duration of controlling the power supply circuit to stop outputting the power supply voltage through the first power supply end reaches the second preset duration.
8. The display device of claim 1, wherein the driver chip includes a first power terminal connected to the second power terminal, the first power terminal configured to power the driver chip through a backlight power supply voltage provided by the second power terminal when the driver chip is in an addressing mode.
9. The display device according to claim 8, wherein the driving chip further comprises a switching unit connected to the first power supply terminal and the driving circuit of the driving chip, respectively; the driving chip is configured to: controlling the switch unit to be in a conducting state under the condition that the driving chip is in an addressing mode so as to conduct a passage between the first power supply end and the second power supply end; And under the condition that the driving chip exits from the addressing mode, controlling the switch unit to be in an off state so as to disconnect a passage between the first power supply end and the second power supply end.
10. The display device of claim 1, wherein the driving chip includes a second power supply terminal, and the first delay circuit includes: the first end of the resistor is connected with the second power supply end of a third driving chip, and the third driving chip is the last driving chip of the first driving chip; and the first end of the capacitor is respectively connected with the second end of the resistor and the second power end of the first driving chip, the second end of the capacitor is grounded, and the capacitor is in a charging state within the delay time.

Description

Display device Technical Field The application relates to the technical field of display, in particular to a display device. Background Display devices can be used to display image or video content and are widely used in daily life. The display apparatus may include a display panel, a backlight assembly, and a controller, and the backlight assembly may include a plurality of driving chips and a plurality of light emitting devices. In order to reduce occupation of an I/O (Input/Output) port of the controller, a plurality of driver chips are generally connected in series to control the plurality of driver chips through one I/O port. The cost of current display devices is still high. Disclosure of Invention Some embodiments of the application disclose a display device that is low cost. Some embodiments of the application provide a display device comprising: a power circuit including a first power supply terminal configured to provide a power supply voltage and a second power supply terminal configured to provide a backlight power supply voltage; m driving units connected in parallel, wherein M is an integer greater than 1; The first driving unit comprises N driving chips which are connected in series, wherein the first driving unit is any driving unit in the M driving units, and N is an integer greater than or equal to 1; The first light-emitting unit corresponding to the first driving unit comprises N light-emitting subunits, the N light-emitting subunits correspond to the N driving chips, and each light-emitting subunit is configured to emit light under the driving of the corresponding driving chip; the M delay circuits correspond to the M driving units, and a first delay circuit corresponding to the first driving unit is connected with a first driving chip of the first driving unit; The first delay circuit is configured to receive the power supply voltage provided by the first power supply terminal simultaneously with a first driving chip of the first driving unit, and provide the power supply voltage to the first driving chip and a driving chip positioned below the first driving chip after a delay time period; a second driving chip configured to: The second driving chip is the first driving chip or the driving chip positioned below the first driving chip, the positions of the second driving chips for sending the addressing trigger signals in the M driving units are different, and/or the delay time lengths of delay circuits corresponding to the M driving units are different; the first driver chip is configured to: outputting a first instruction to other driving units under the condition that the first driving chip receives the addressing trigger signal; Determining address data corresponding to the first driving chip according to the first number of the acquired first instructions, and sending the address data corresponding to the first driving chip to the next driving chip; The P-th driving chip in the first driving unit is configured to: Receiving address data corresponding to a last driving chip sent by the last driving chip; And determining address data corresponding to the P-th driving chip according to the address data corresponding to the last driving chip, and sending the address data corresponding to the P-th driving chip to the next driving chip until the P-th driving chip is the last driving chip of the first driving unit, wherein P is an integer greater than 1 and less than or equal to N. In some embodiments of the present application, the display device includes a power supply circuit, M driving units, M light emitting units, and M delay circuits, where, when the first power supply terminal provides the power supply voltage, the first driving chip and the first delay circuit receive the power supply voltage at the same time, and after a delay period corresponding to the first delay circuit, the second driving chip receives the power supply voltage, and because a position of the second driving chip in the M driving units is different, and/or a delay period corresponding to the M delay circuits is different, a time when the first driving chip in each driving unit receives the address trigger signal is different. When the first driving chip receives the addressing trigger signal, a first instruction is output, and as the moments that the driving chips receive the addressing trigger signal are different, the number of the first instructions received by the first driving chip in different driving units is different, the first driving chip determines address data corresponding to the first driving chip according to the number of the acquired first instructions, so that the address data corresponding to the first driving chip belonging to different driving units is different, and as the P driving chip determines the address data corresponding to the P driving chip according to the address data corresponding to the last driving chip, the address data corresponding to the P driving chip is also differen