CN-122024663-A - Gate driving circuit and display device

CN122024663ACN 122024663 ACN122024663 ACN 122024663ACN-122024663-A

Abstract

The application provides a gate driving circuit and a display device. The grid driving circuit comprises a plurality of cascaded grid driving units, wherein each grid driving unit comprises an output module and a pull-up node, each output module comprises a first output end and a second output end, the first output end is used for outputting a current-stage transmission signal, the second output end is used for outputting a current-stage grid scanning signal, the pull-up node is connected with a control end of the output module, the control module is connected between the pull-up node and the output module and controls on-off of the pull-up node and the output module based on the control signal, and accordingly the output state of the second output end is adjusted, and dynamic adjustment of intra-frame frequency is achieved. The control module is connected between the pull-up node and the output module, and the on-off structure is adjusted based on the control signal, so that the mechanism of realizing dynamic adjustment of the partition frequency in the frame is realized, and the power consumption of the display area is reduced.

Inventors

SHU QIANG
DAI WENJUN
CAO ZHENPENG
XU PEI

Assignees

惠科股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260213

Claims (10)

1. A gate driving circuit comprising a plurality of cascaded gate driving units, the gate driving units comprising: The output module comprises a first output end and a second output end, wherein the first output end is used for outputting a current stage signal, and the second output end is used for outputting a current stage grid scanning signal; The pull-up node is connected with the control end of the output module; The grid driving unit is characterized by further comprising a control module, wherein the control module is connected between the pull-up node and the output module and controls on-off between the pull-up node and the output module based on a control signal so as to adjust the output state of the second output end and realize dynamic adjustment of the frequency in a frame.
2. The gate driving circuit according to claim 1, wherein the gate driving circuit comprises N gate driving units, which are respectively in one-to-one correspondence with N row scanning lines, for progressive scanning, the gate driving units being configured to: In response to driving a corresponding row scan line at a first refresh rate, the control module receives a first set of control signals to turn on the pull-up node and the output module, the first output terminal and the second output terminal both being in a scan state; in response to driving a corresponding row scan line at a second refresh rate, the control module receives a second set of control signals to disconnect the pull-up node from the output module, the first output is in a scan state, the second output is in a inhibit state, and an invalid level is output; Wherein the first refresh rate is higher than the second refresh rate.
3. The gate driving circuit according to claim 2, wherein the gate driving circuit comprises k clock signals with different phases, each stage of the gate driving unit is sequentially and circularly connected with the k clock signals; the output module is connected with a clock signal and synchronously outputs the level transmission signal when the clock signal is in an effective level; The grid driving unit further comprises an input module, wherein the input module is connected with the pull-up node and is configured to precharge the pull-up node to a high level under the triggering of a frame starting signal or a previous k/2-level signaling signal; The gate driving units connected to the same clock signal receive the same control signal, and the level combinations of the first control signal group and the second control signal group are opposite to each other.
4. A gate driving circuit according to claim 3, wherein the start time of the active state of the second control signal group is advanced from the preset output on time of the corresponding gate driving unit by a time length less than or equal to T/2 and greater than T/k-W, where T is the period of the clock signal and W is the active level pulse width of the clock signal.
5. The gate drive circuit of claim 4, wherein in the intra-frame time multi-frequency drive mode, each frame of picture is divided into a first partition and a second partition along a scanning direction, the gate drive unit corresponding to the first partition is refreshed at a first refresh rate; the duration of the effective state of the second control signal group is a preset value, and the preset value is the scanning duration corresponding to the second partition.
6. The gate drive circuit of claim 2, wherein the output module comprises a first path for coupling a clock signal to the first output terminal and a second path for coupling the clock signal to the second output terminal; The control module is connected between the pull-up node and the control end of the second path so as to control the on-off of the second path; The control module is also connected between a low level signal and the second output end, and is also connected between the low level signal and the control end of the second path, so that the second output end outputs an invalid level in response to the second control signal group.
7. The gate drive circuit of claim 6, wherein the gate drive unit further comprises a first capacitor and a second capacitor, the first capacitor being connected between the pull-up node and the first output terminal; the second capacitor is connected between the control end of the second path and the second output end.
8. The gate drive circuit of claim 6, wherein the control module comprises a first control switch, a second control switch, and a third control switch, The first control switch is connected between the low-level signal and the control end of the second path, and the control end of the first control switch receives a first control signal; the second control switch is connected between the pull-up node and the control end of the second path, and the control end of the second control switch receives a second control signal; The third control switch is connected between the low-level signal and the second output end, and the control end of the third control switch receives the first control signal; The first control signal group and the second control signal group are composed of the first control signal and the second control signal.
9. The gate driving circuit of claim 8, wherein the first control switch, the second control switch and the third control switch are all the same in conduction type, the first control signal and the second control signal are opposite in phase, or, The first control switch and the third control switch are the same in conduction type, opposite to the second control switch in conduction type, and the first control signal and the second control signal are the same in phase or the same in signal.
10. A display device comprising a plurality of rows of scanning lines and the gate driving circuit according to any one of claims 1 to 9; The gate driving circuit is used for driving the plurality of rows of scanning lines.

Description

Gate driving circuit and display device Technical Field The present application relates to the field of display technologies, and in particular, to a gate driving circuit and a display device. Background With the development of liquid crystal display technology, low power consumption requirements are increasingly demanded. Therefore, a display area division driving concept is proposed. Disclosure of Invention The application mainly solves the technical problem of providing a grid driving circuit and a display device, and solves the problem of how to realize frequency division driving of a display area. In order to solve the technical problem, a first technical scheme provided by the application is that a gate driving circuit is provided, which comprises a plurality of cascaded gate driving units, wherein the gate driving units comprise: The output module comprises a first output end and a second output end, wherein the first output end is used for outputting a current level transmission signal, and the second output end is used for outputting a current level grid scanning signal; The pull-up node is connected with the control end of the output module; the grid driving unit further comprises a control module, wherein the control module is connected between the pull-up node and the output module and controls on-off between the pull-up node and the output module based on a control signal so as to adjust the output state of the second output end and realize dynamic adjustment of the frequency in the frame. In some embodiments, the gate driving circuit includes N gate driving units corresponding to N row scanning lines one by one for progressive scanning, respectively, wherein the gate driving units are used for: responding to the driving of the corresponding row scanning lines at a first refresh rate, and receiving a first control signal group by the control module so as to conduct the pull-up node and the output module, wherein the first output end and the second output end are both in a scanning state; Responding to the driving of the corresponding row scanning lines at the second refresh rate, and receiving a second control signal group by the control module so as to disconnect the pull-up node from the output module, wherein the first output end is in a scanning state, the second output end is in a suppression state and an invalid level is output; Wherein the first refresh rate is higher than the second refresh rate. In some embodiments, the gate driving circuit comprises k clock signals with different phases, wherein each stage of gate driving unit is sequentially and circularly connected with the k clock signals; the output module is connected with a clock signal and synchronously outputs the level transmission signal when the clock signal is at an effective level; The grid driving unit further comprises an input module, wherein the input module is connected with the pull-up node and is configured to precharge the pull-up node to a high level under the triggering of a frame starting signal or a previous k/2 level signaling signal; the grid driving units connected to the same clock signal receive the same control signal, and the level combinations of the first control signal group and the second control signal group are mutually opposite. In some embodiments, the start time of the active state of the second control signal group is advanced from the preset output on time of the corresponding gate driving unit, and the advanced time period is less than or equal to T/2 and greater than T/k-W, where T is the period of the clock signal and W is the active level pulse width of the clock signal. In some embodiments, in an intra-frame time-division multi-frequency driving mode, each frame of picture is divided into a first partition and a second partition along a scanning direction, wherein a grid driving unit corresponding to the first partition is refreshed at a first refresh rate; The duration of the effective state of the second control signal group is a preset value, and the preset value is the scanning duration of the corresponding second partition. In some embodiments, the output module includes a first path for coupling the clock signal to the first output and a second path for coupling the clock signal to the second output; the control module is connected between the pull-up node and the control end of the second path so as to control the on-off of the second path; the control module is also connected between the low level signal and the second output end, and is also connected between the low level signal and the control end of the second path, so that the second output end outputs an invalid level in response to the second control signal group. In some embodiments, the gate driving unit further includes a first capacitor and a second capacitor, the first capacitor being connected between the pull-up node and the first output terminal; The second capacitor is connected between the control end of the seco