CN-122024778-A - Memory array circuit capable of executing logic shift operation and memory

CN122024778ACN 122024778 ACN122024778 ACN 122024778ACN-122024778-A

Abstract

The application provides a memory array circuit and a memory capable of executing logic shift operation, which are characterized in that the sense amplifying circuit is connected to a corresponding bit line of a column, the sense amplifying circuit is connected to the corresponding bit line through a disconnecting switch, a shift switch is arranged between the sense amplifying circuit and the bit line of another column, the disconnecting switch is conducted in a first period of time when the sense amplifying circuit executes logic shift operation, so that stored data stored in a first memory cell which is turned on the corresponding bit line is transferred to the sense amplifying circuit through the corresponding bit line and the conducting disconnecting switch to be latched in the sense amplifying circuit, the shift switch is conducted in a second period of time, and the stored data latched by the sense amplifying circuit is shifted to a second memory cell which is turned on the bit line of another column through the conducting shift switch and stored, thereby realizing logic shift operation in the memory.

Inventors

NIU JIANING
MA JIAYI

Assignees

西安芯存半导体有限公司
珠海横琴芯存半导体有限公司
合肥芯存半导体有限公司
上海芯存志远半导体有限公司
北京芯存集成电路有限公司

Dates

Publication Date: 20260512
Application Date: 20251210

Claims (11)

1. A memory array circuit capable of performing a logical shift operation, comprising a plurality of sense amplifying units, each of the sense amplifying units comprising: a sense amplifier circuit configured to connect a row of corresponding bit lines; The sense amplifying circuit is connected with the corresponding bit line through the isolating switch; A shift switch connected between the sense amplifying circuit and another column of bit lines; in response to the sense amplifying circuit executing a logic shift operation, the isolating switch is conducted in a first period, and stored data stored in the turned-on first storage unit on the corresponding bit line is transferred to the sense amplifying circuit through the corresponding bit line and the conducted isolating switch so as to be latched in the sense amplifying circuit; the shift switch is conducted in a second period, and the stored data latched by the sense amplifying circuit is shifted to an opened second memory cell on the other column of bit lines through the conducted shift switch and stored.
2. The memory array circuit of claim 1, wherein, Another column of the bit lines is located on the right side of the corresponding bit line, the logical shift operation is a logical right shift operation, or Another column of the bit lines is left of the corresponding bit line, the logical shift operation is a logical left shift operation, or The shift switch in each of the sense amplifying units includes: a first shift switch connected between the sense amplifying circuit and the other column of bit lines; a second shift switch connected between the sense amplifying circuit and the further column of bit lines; wherein the other column of bit lines is located on the right side of the corresponding bit line, the further column of bit lines is located on the left side of the corresponding bit line, and the logical shift operation comprises a logical right shift operation and a logical left shift operation.
3. The memory array circuit of claim 2, wherein, Another column of the bit lines is a column of bit lines adjacent to the right side of the corresponding bit line, or Another column of the bit lines is an adjacent column of bit lines on the left side of the corresponding bit line, or The other column of bit lines is a column of bit lines adjacent to the right side of the corresponding bit line, and the other column of bit lines is a column of bit lines adjacent to the left side of the corresponding bit line.
4. The memory array circuit of claim 1, wherein, The second period of time is not earlier than the first period of time, or The second period is later than the first period, and the second period does not have an overlapping portion with the first period.
5. The memory array circuit of claim 4, wherein, The first memory cell and the second memory cell are connected to the same row word line.
6. The memory array circuit of claim 5, wherein, The first and second memory cells have overlapping portions of a period in which the first and second memory cells are turned on and the first and second periods, respectively.
7. The memory array circuit of claim 1, wherein, The first storage unit and the second storage unit are storage units in a first storage area respectively; The sense amplifying circuit is further connected to a second memory region to provide a sense amplifying function for memory cells in the second memory region, wherein bit lines in the second memory region are respectively used as inverted bit lines of corresponding bit lines in the first memory region.
8. The memory array circuit of claim 7, wherein, Each of the sense amplifying units in the sense amplifying circuit further comprises a disconnecting switch and a shifting switch for the second storage area, so as to provide executable logic shifting operation for the second storage area, wherein the disconnecting switch and the shifting switch for the second storage area and the disconnecting switch and the shifting switch for the first storage area are symmetrically arranged with each other, and the disconnecting switch and the shifting switch for the second storage area serve as a reverse disconnecting switch and a reverse shifting switch for the disconnecting switch and the shifting switch for the first storage area respectively; The other column of bit lines in the first storage area is located on the first side of the corresponding bit lines, the other column of bit lines in the second storage area is also located on the first side of the corresponding bit lines, wherein the bit lines corresponding to the second storage area serve as inverted bit lines of the bit lines corresponding to the first storage area, and the other column of bit lines in the second storage area serve as inverted bit lines of the other column of the first storage area.
9. The memory array circuit of claim 8, wherein, In response to the memory array circuit performing a logic shift operation towards a first side for the first memory region, the isolation switch for the first memory region is turned on for a first period, stored data stored by the first memory cells turned on the corresponding bit lines in the first memory region is transferred to the sense amplifying circuit to be latched at a first input end of the sense amplifying circuit; In response to the memory array circuit performing a logic shift operation towards a second side for the first memory region, the isolation switch for the first memory region is turned on for a first period of time, memory data stored by the first memory cells turned on the corresponding bit lines in the first memory region is transferred to the sense amplifying circuit to be latched at a first input terminal of the sense amplifying circuit, a second input terminal of the sense amplifying circuit senses the first input terminal to generate sensing data, and the corresponding bit lines in the second memory region read the sensing data; the reverse shift switch in the sense amplifying unit in the second side direction is turned on in a second period, the sensing data on the corresponding reverse bit line in the second storage area is shifted to an on third memory cell on a further column of reverse bit lines connected to the sense amplifying unit in the second side direction, the reverse isolation switch in the sense amplifying unit in the second side direction is turned on in a third period, the sensing data stored in the third memory cell on the further column of reverse bit lines is transferred to a second input terminal of the sense amplifying circuit in the sense amplifying unit in the second side direction, a first input terminal of the sense amplifying circuit senses the sensing data of the second input terminal to restore the storage data and latch, the isolation switch in the sense amplifying unit in the second side direction is turned on in a fourth period, the storage data of the first input terminal of the sense amplifying circuit is transferred to the corresponding fourth memory cell on the sense amplifying unit in the second side direction, to complete the logical shift operation towards the second side for the first storage region.
10. The memory array circuit of claim 9, wherein the memory array circuit comprises a plurality of memory cells, The sense amplifier circuit is configured to sense a sense voltage on the bit line and a reference voltage on the inverted bit line.
11. A memory comprising the memory array circuit of any one of claims 1-10.

Description

Memory array circuit capable of executing logic shift operation and memory Technical Field The disclosed embodiments of the application relate to the field of memory technology, and more particularly, to a memory array circuit and memory that can perform logical shift operations. Background In the traditional von neumann architecture, the separation of the processor from the memory causes frequent data movement, causes a 'memory wall' problem, is limited in computing efficiency by the memory access speed, and has extremely high data handling energy consumption ratio. The scenes such as artificial intelligence, edge computing and the like rely on high-parallelism and low-power-consumption real-time processing, so that the defects of the traditional architecture are further exposed. In order to increase the memory access speed and reduce the power consumption, in-memory operations have been developed, for example, in which a logical and operation or a bit-wise inverting operation is performed in memory, but there is no technology capable of performing a logical shift operation in memory. Disclosure of Invention According to an embodiment of the application, a memory array circuit and a memory capable of performing a logical shift operation are provided to realize the execution of the logical shift operation in the memory. In one aspect, the present application provides a memory array circuit capable of performing a logical shift operation, including a plurality of sense amplifying units, each of the sense amplifying units includes a sense amplifying circuit, an isolating switch, and a shift switch, respectively. The sensing amplifying circuit is connected with a corresponding bit line of a column, the sensing amplifying circuit is connected with the corresponding bit line through a disconnecting switch, a shifting switch is connected between the sensing amplifying circuit and the bit line of the other column, the disconnecting switch is conducted in a first period in response to the sensing amplifying circuit executing logic shifting operation, storage data stored in an opened first storage unit on the corresponding bit line is transferred to the sensing amplifying circuit through the corresponding bit line and the conducting disconnecting switch to be latched in the sensing amplifying circuit, the shifting switch is conducted in a second period, and the storage data latched by the sensing amplifying circuit is shifted to an opened second storage unit on the bit line of the other column through the conducting shifting switch and stored. A second aspect of the application provides a memory comprising the memory array circuitry of the first aspect. According to the scheme, through the sense amplifying circuit connected to the corresponding bit line of one column, the sense amplifying circuit is connected to the corresponding bit line through the isolating switch, the shift switch is arranged between the sense amplifying circuit and the bit line of the other column, the isolating switch is conducted in the first period of time when the sense amplifying circuit executes logic shift operation, so that stored data stored in the first storage unit on the corresponding bit line is transferred to the sense amplifying circuit through the corresponding bit line and the conducting isolating switch to be latched in the sense amplifying circuit, the shift switch is conducted in the second period of time, and the stored data latched by the sense amplifying circuit is shifted to the second storage unit on the bit line of the other column through the conducting shift switch and stored, and therefore logic shift operation is achieved in the memory. Drawings The application will be further described with reference to the accompanying drawings and embodiments, in which: FIG. 1 is a schematic diagram of a frame of some embodiments of a memory array circuit of the present application; FIG. 2 is a schematic diagram of a frame of another embodiment of a memory array circuit of the present application; FIG. 3 is a schematic diagram of a frame of still further embodiments of a memory array circuit of the present application; FIG. 4 is a schematic diagram of a frame of still other embodiments of a memory array circuit of the present application; FIG. 5 is a schematic diagram of a frame of still other embodiments of a memory array circuit of the present application; FIG. 6 is a schematic diagram of a frame of some embodiments of the memory of the present application; FIG. 7 is a timing diagram illustrating a logic shift operation performed according to some embodiments of the present application; FIG. 8 is a schematic diagram of the result of the memory of FIG. 6 after performing a logical right shift operation. Reference numerals illustrate 1000, a memory array circuit, 1100, a sense amplifying unit, 1120, a disconnecting switch, 1110, a sense amplifying circuit, 1130, a shift switch, 11, a first memory unit, 12, a second memory unit,