CN-122024779-A - Equivalent analog circuit of memory transistor

CN122024779ACN 122024779 ACN122024779 ACN 122024779ACN-122024779-A

Abstract

The invention relates to the technical field of circuit design and discloses an equivalent analog circuit of a memory transistor, which comprises a drain electrode input end d, a grid electrode input end g, seven operational amplifiers, three multipliers and a plurality of resistance-capacitance elements. The drain input signal is processed by a differential and integral circuit to generate a state variable, and then is subjected to nonlinear transformation by an evolution and addition circuit, and the gate input signal is subjected to threshold operation by a subtraction and addition circuit. The two paths of signals are subjected to cascade operation through a multiplier and then are subjected to feedback superposition with the drain electrode signals, so that final drain electrode current is formed. The invention accurately realizes the physical model of the memory transistor through the universal analog device, can output a typical pinch hysteresis loop, and has the gate voltage regulation and control characteristic. The circuit has the advantages of low cost, adjustable parameters, easy construction and the like, and can effectively replace a nanoscale physical device to be used for experimental study of nonvolatile storage and nerve morphology calculation.

Inventors

XU BIRONG
Ye Ximei

Assignees

武夷学院

Dates

Publication Date: 20260512
Application Date: 20260202

Claims (10)

1. The equivalent analog circuit of the memory transistor is characterized by comprising a drain electrode input end D, a grid electrode input end g, a source electrode input end s, seven operational amplifiers U1 to U7, three multipliers A1 to A3, a capacitor C1, a diode D1, twenty-three resistors R1 to R23, a direct-current voltage source V1, a direct-current voltage source V2, a direct-current voltage source V3 and a direct-current voltage source Vth, wherein the source electrode input end s is grounded; The operational amplifier U1, the resistor R1 and the resistor R5 form a first differential circuit, and the input end of the first differential circuit is respectively connected with the drain electrode input end d and the output end of the operational amplifier U4; The operational amplifier U2, the resistor R6 and the capacitor C1 form a first integrating circuit, and the input end of the first integrating circuit is connected with the output end of the operational amplifier U1; the operational amplifier U3, the multiplier A1, the diode D1 and the resistor R7 to the resistor R9 form a first squaring circuit, and the input end of the first squaring circuit is connected with the output end of the operational amplifier U2; The operational amplifier U5, the resistor R13 and the resistor R16 form a first addition circuit, and the input end of the first addition circuit is respectively connected with the output end of the first squaring circuit, the direct-current voltage source V1 and the direct-current voltage source V2; The operational amplifier U6, the resistor R17 to the resistor R20 form a first subtracting circuit, and the input end of the first subtracting circuit is respectively connected with the gate input end g and the dc voltage source Vth; The operational amplifier U7, the resistor R21 and the resistor R23 form a second addition circuit, and the input end of the second addition circuit is respectively connected with the output end of the operational amplifier U6 and the direct-current voltage source V3; The multiplier A2 and the multiplier A3 form a multiplication circuit, and the multiplication circuit is respectively connected with the second addition circuit, the first addition circuit and the output end of the operational amplifier U1; The operational amplifier U4, the resistor R10 and the resistor R12 form a third adding circuit, the input end of the third adding circuit is respectively connected with the output end of the multiplication circuit and the output end of the operational amplifier U1, and the output end of the third adding circuit is connected with the resistor R1.
2. The memory transistor equivalent analog circuit according to claim 1, wherein in said first differential circuit, one end of said resistor R1 is connected to said drain input terminal d, the other end of said resistor R1 is connected to one end of said resistor R2 and the output terminal of said operational amplifier U4, respectively, the other end of said resistor R2 is connected to the inverting terminal of said operational amplifier U1, one end of said resistor R3 is connected to said drain input terminal d, the other end of said resistor R3 is connected to the non-inverting terminal of said operational amplifier U1, both ends of said resistor R4 are connected to the non-inverting terminal of said operational amplifier U1 and the output terminal of said operational amplifier U1, respectively, one end of said resistor R5 is connected to the non-inverting terminal of said operational amplifier U1, and the other end of said resistor R5 is grounded.
3. The memory transistor equivalent analog circuit according to claim 1, characterized in that in said first integrating circuit, one end of said resistor R6 is connected to an output end of said operational amplifier U1, the other end of said resistor R6 is connected to an inverting end of said operational amplifier U2, both ends of said capacitor C1 are respectively connected to an inverting end of said operational amplifier U2 and an output end of said operational amplifier U2, and an in-phase end of said operational amplifier U2 is grounded.
4. The memory transistor equivalent analog circuit according to claim 1, characterized in that in said first squaring circuit, one end of said resistor R7 is connected to an output end of said operational amplifier U2, the other end of said resistor R7 is connected to an inverting end of said operational amplifier U3, one end of said resistor R8 is connected to an inverting end of said operational amplifier U3, the other end of said resistor R8 is connected to an output end of said multiplier A1, one end of said resistor R9 is connected to an in-phase end of said operational amplifier U3, the other end of said resistor R9 is grounded, an output end of said operational amplifier U3 is connected to an anode of said diode D1, a cathode of said diode D1 is simultaneously connected to an X end of said multiplier A1 and a Y end of said multiplier A1, and an output end of said multiplier A1 is connected to the other end of said resistor R8.
5. The memory transistor equivalent analog circuit according to claim 1, characterized in that in said first adder circuit, one end of said resistor R15 is connected to the cathode of said diode D1, the other end of said resistor R15 is connected to the inverting terminal of said operational amplifier U5, one end of said resistor R14 is connected to the inverting terminal of said operational amplifier U5, the other end of said resistor R14 is connected to the negative terminal of said DC voltage source V1, the positive terminal of said DC voltage source V1 is grounded, one end of said resistor R16 is connected to the inverting terminal of said operational amplifier U5, the other end of said resistor R16 is connected to the positive terminal of said DC voltage source V2, the negative terminal of said DC voltage source V2 is grounded, the two ends of said resistor R13 are respectively connected to the inverting terminal of said operational amplifier U5 and the output terminal of said operational amplifier U5, and the same phase terminal of said operational amplifier U5 is grounded.
6. The memory transistor equivalent analog circuit according to claim 1, characterized in that in said first subtracting circuit, one end of said resistor R17 is connected to an inverting terminal of said operational amplifier U6, the other end of said resistor R17 is connected to an anode terminal of said DC voltage source Vth, a cathode terminal of said DC voltage source Vth is grounded, one end of said resistor R18 is connected to said gate input terminal g, the other end of said resistor R18 is connected to an in-phase terminal of said operational amplifier U6, one end of said resistor R20 is connected to an in-phase terminal of said operational amplifier U6, the other end of said resistor R20 is grounded, and both ends of said resistor R19 are connected to an inverting terminal of said operational amplifier U6 and an output terminal of said operational amplifier U6, respectively.
7. The memory transistor equivalent analog circuit according to claim 1, characterized in that in said second adder circuit, one end of said resistor R21 is connected to an output end of said operational amplifier U6, the other end of said resistor R21 is connected to an inverting end of said operational amplifier U7, one end of said resistor R22 is connected to an inverting end of said operational amplifier U7, the other end of said resistor R22 is connected to a negative end of said DC voltage source V3, an anode of said DC voltage source V3 is grounded, both ends of said resistor R23 are respectively connected to an inverting end of said operational amplifier U7 and an output end of said operational amplifier U7, and a same-phase end of said operational amplifier U7 is grounded.
8. The memory transistor equivalent analog circuit according to claim 1, wherein in said multiplication circuit, an X end of said multiplier A3 is connected to an output end of said operational amplifier U7, a Y end of said multiplier A3 is connected to an output end of said operational amplifier U5, an output end of said multiplier A3 is connected to an X end of said multiplier A2, a Y end of said multiplier A2 is connected to an output end of said operational amplifier U1, and an output end of said multiplier A2 is connected to one end of said resistor R12.
9. The memory transistor equivalent analog circuit according to claim 8, characterized in that in said third adder circuit, an inverting terminal of said operational amplifier U4 is connected to one end of said resistor R11 and the other end of said resistor R12, respectively, the other end of said resistor R11 is connected to an output terminal of said operational amplifier U1, one end of said resistor R12 is connected to an output terminal of said multiplier A2, an in-phase terminal of said operational amplifier U4 is grounded, and both ends of said resistor R10 are connected to an inverting terminal of said operational amplifier U4 and an output terminal of said operational amplifier U4, respectively.
10. The memory transistor equivalent analog circuit according to claim 1, wherein the resistance of the resistor R2 is equal to the resistance of the resistor R3, the resistance of the resistor R4 is equal to the resistance of the resistor R5, the resistance of the resistor R7 is equal to the resistance of the resistor R8, the resistance of the resistor R9 is equal to the resistance of the resistor R7 and the resistor R8 after being connected in parallel, the resistance of the resistor R13 is equal to the resistance of the resistor R16, the resistance of the resistor R17, the resistance of the resistor R18, the resistance of the resistor R19, and the resistance of the resistor R20 are equal, and the resistance of the resistor R22 is equal to the resistance of the resistor R23.

Description

Equivalent analog circuit of memory transistor Technical Field The invention relates to the technical field of circuit design, in particular to an equivalent analog circuit of a memory transistor. Background The memory transistor is a novel multi-terminal electronic device with the nonvolatile resistance change characteristic of the memristor and the gate control characteristic of the field effect transistor. The device is generally composed of a source electrode, a drain electrode and a grid electrode, and is characterized in that the conductance of a drain-source channel not only depends on the current bias voltage, but also is related to the historical electrical state of the device, and meanwhile, the grid electrode voltage can effectively regulate the resistance variation behavior of the channel. In terms of electrical characteristics, the memory transistor shows a typical pinch hysteresis loop, and the unique nonlinear dynamics behavior enables the memory transistor to simulate the weight updating and adjusting functions of biological synapses, so that the memory transistor has important application potential in the aspects of constructing a high-density nonvolatile memory and a brain-like nerve morphology computing system. In the prior art, the physical implementation of a memory transistor mainly depends on advanced nanomaterial science and micro-nano processing technology. Researchers generally adopt two-dimensional materials such as molybdenum disulfide, graphene and the like or transition metal oxides as channel media, combine ferroelectric films or charge trapping layers to construct a grid stacking structure, and prepare nanoscale devices through semiconductor manufacturing technologies such as physical vapor deposition, atomic layer deposition, electron beam lithography and the like. In practical application research, such nano-devices are often utilized to replicate long-term enhancement and suppression of synaptic plasticity behavior by ion migration or charge trapping mechanisms, and are integrated into an array architecture to verify the feasibility of in-memory computing architecture. However, the requirements of the process environment and equipment precision of the memory transistor based on the nano-film material in the preparation process are extremely high. Because of the complicated material interface engineering and the nanoscale patterning process, the preparation flow of the device is complicated and extremely sensitive to the tiny fluctuation of the process parameters, which results in lower yield of the device and obvious discreteness of the electrical parameters among different batches. The dependence on high nano processing facilities and the high difficulty of the preparation process make the memory transistor sample with stable performance and good consistency difficult to obtain at low cost, thereby seriously impeding the extensive and deep experimental study on the application characteristics of the memory transistor sample in a circuit and system layer. Disclosure of Invention In order to overcome the defects in the prior art, the invention provides an equivalent analog circuit of a memory transistor, which solves the problems mentioned in the background art. The invention is realized by the following technical scheme that the memory transistor equivalent analog circuit is constructed based on a general integrated operational amplifier, an analog multiplier and a passive device, and aims to simulate the electrical characteristics of a nanoscale memory transistor through a macroscopic hardware circuit. The memory transistor equivalent analog circuit comprises a drain electrode input end D, a gate electrode input end g, a source electrode input end s, seven integrated operational amplifiers U1 to U7, three analog multipliers A1 to A3, a capacitor C1, a diode D1, twenty-three resistors R1 to R23 and direct-current voltage sources V1, V2, V3 and Vth, wherein the source electrode input end s is grounded. In specific topological connection of the circuit, an operational amplifier U1 is matched with resistors R1 to R5 to form a differential operation unit, the input end of the operational amplifier U1 is connected with a drain input end D and is used for extracting drain-source voltage signals, an integral operation unit is formed by the operational amplifier U2, a resistor R6 and a capacitor C1, time integration is carried out on output signals of the operational amplifier U1, state variable signals representing a resistance change mechanism inside a memory transistor are generated, an evolution operation unit is formed by the operational amplifier U3, a multiplier A1, a diode D1 and resistors R7 to R9 and is used for carrying out nonlinear transformation on the state variable signals, an addition operation unit is formed by the operational amplifier U5 matched with resistors R13 to R16 and direct current voltage sources V1 and V2, and direct current bias processing is carried