CN-122024781-A - Circuit structure, data reading and writing method, memory and electronic equipment

Abstract

The embodiment of the application provides a circuit structure, a data reading and writing method, a memory and electronic equipment, and relates to the technical field of semiconductors. The circuit structure comprises at least one group of switch units, wherein each group of switch units comprises at least two first switch modules and at least two second switch modules, and the circuit structure is used for conducting the first ends and the second ends of the corresponding first switch modules, disconnecting the first ends and the second ends of the corresponding second switch modules and applying a first control voltage to the corresponding second control signal lines so that target storage units corresponding to the word lines share charges of the bit lines and data are read and written. The circuit structure of the embodiment of the application realizes that the control signals required by the gating of the word lines are reduced, and the control complexity is reduced.

Inventors

• HUANG CHUANHUI

Assignees

• 北京超弦存储器研究院

Dates

Publication Date

20260512

Application Date

20241112

Claims (18)

1. 1. The circuit structure is characterized by comprising at least one group of switch units, wherein each group of switch units comprises at least two first switch modules and at least two second switch modules; the control end and the first end of each first switch module are respectively and correspondingly electrically connected with a first control signal line and a second control signal line, and the second end of each first switch module is used for being electrically connected with at least one word line; The control end and the first end of each second switch module are respectively and correspondingly electrically connected with a third control signal line and a fourth control signal line, and the second end of each second switch module is used for being correspondingly and electrically connected with at least one word line; the first ends of the at least two first switch modules arranged along the first direction are correspondingly and electrically connected with the same second control signal line; In each group of switch units, the control ends of at least two first switch modules arranged along a second direction are correspondingly and electrically connected with the same first control signal line, and the control ends of at least two second switch modules arranged along the second direction are correspondingly and electrically connected with the same third control signal line; the circuit structure is used for conducting the first end and the second end of the corresponding first switch module, disconnecting the first end and the second end of the corresponding second switch module and applying the first control voltage to the corresponding second control signal line in an activation stage aiming at the selected word line, so that the target storage unit corresponding to the word line is shared with the bit line charge, and data reading and writing are performed.
2. 2. The circuit structure of claim 1, wherein the circuit structure is configured to disconnect the first and second terminals of each of the first switch modules, and to connect the first and second terminals of each of the second switch modules, and to apply a second control voltage to each of the fourth control signal lines during the precharge phase, such that the memory devices of the memory cells are electrically disconnected from the bit lines; Wherein one of the first control voltage and the second control voltage is at a high level and one of the first control voltage and the second control voltage is at a low level, and the precharge phase is located before the activation phase and/or after the activation phase.
3. 3. The circuit structure according to claim 1, wherein first ends of one row of the first switch modules arranged in the first direction are electrically connected to the same one of the second control signal lines; the control ends of a group of first switch modules arranged along the second direction are correspondingly and electrically connected with the same first control signal line, and the control ends of a group of second switch modules arranged along the second direction are correspondingly and electrically connected with the same third control signal line.
4. 4. The circuit structure of claim 1, wherein the first switch module comprises a first switch device having a gate as a control terminal of the first switch module, one of a source and a drain of the first switch device being a first terminal of the first switch module and the other being a second terminal of the first switch module; The second switch module comprises a second switch device, wherein a grid electrode of the second switch device is used as a control end of the second switch module, and one of a source electrode and a drain electrode of the second switch device is used as a first end of the second switch module, and the other of the source electrode and the drain electrode of the second switch device is used as a second end of the second switch module.
5. 5. The circuit structure of claim 4, wherein the first switching device and the second switching device are NMOS transistors or wherein the first switching device and the second switching device are PMOS transistors.
6. 6. The circuit structure of claim 4, wherein the first switching device is a PMOS transistor and the second switching device is an NMOS transistor, or wherein the first switching device is an NMOS transistor and the second switching devices are all PMOS transistors; The control signals output by the first control signal line and the third control signal line are the same.
7. 7. The circuit structure of claim 6, wherein each word line is electrically connected to one of the first switch modules and one of the second switch modules, respectively; In the first switch module and the second switch module connected to the same word line, a first control signal line electrically connected to the first switch module and a third control signal line electrically connected to the second switch module are electrically connected to receive the same control signal.
8. 8. The circuit structure according to claim 1, wherein the first control signal line and the third control signal line extend to a side of the switching unit away from the wafer; At least part of the first control signal lines and at least part of the second control signal lines are perpendicular to the wafer.
9. 9. The circuit structure of claim 4, wherein the channel of the first switching device is disposed perpendicular to the wafer and/or the channel of the second switching device is disposed perpendicular to the wafer.
10. 10. The circuit structure of claim 1, wherein the second end of each first switch module is configured to be electrically connected to one word line, the second end of each second switch module is configured to be electrically connected to one word line, and the first switch module and the second switch module are located on two sides of the memory cell in a vertical wafer direction.
11. 11. The circuit structure of claim 1, wherein the first switch module and the second switch module are each located on a side of the memory cell away from the wafer; Every two adjacent word lines are electrically connected through a signal connection line, the signal connection line is at least partially located on one side, close to the wafer, of the memory unit, one word line is electrically connected with the second end of the first switch module, and the other word line is electrically connected with the second end of the second switch module.
12. 12. The circuit structure of claim 1, wherein each of the fourth control signal lines is electrically connected to a first voltage terminal to which a second control voltage is applied, the second control voltage being used to control the opening of the switching device of the memory cell so that the memory device of the memory cell is electrically disconnected from the bit line.
13. 13. The circuit structure of claim 1, further comprising at least one drive module; The first end, the second end, the third end and the fourth end of each driving module are respectively and electrically connected with one second control signal line, one second voltage end, one third voltage end and one fifth control signal line; each driving module is configured to output, in an active stage, an output voltage of the second voltage terminal or an output voltage of the third voltage terminal as the first control voltage through the second control signal line to at least one corresponding word line under control of an output voltage of the fifth control signal line; Wherein, one of the output voltage of the second voltage terminal and the output voltage of the third voltage terminal is at a high level, and the other is at a low level.
14. 14. The circuit structure of claim 13, wherein each of the driving modules includes a third switching device and a fourth switching device; one of a source electrode and a drain electrode of the third switching device is used as a second end of the driving module, and the other is correspondingly and electrically connected with the second control signal line; One of a source electrode and a drain electrode of the fourth switching device is used as a third end of the driving module, and the other is correspondingly and electrically connected with the second control signal line; The grid electrode of the third switching device and the grid electrode of the fourth switching device are used as a fourth end of the driving module together; The third switching device is a PMOS transistor, the fourth switching device is an NMOS transistor, or the third switching device is an NMOS transistor, and the fourth switching devices are all PMOS transistors.
15. 15. A memory comprising a plurality of bit lines, a plurality of word lines, a plurality of memory cells arranged in an array, and the circuit structure of any one of claims 1-14; one of the bit lines is electrically connected with one row of the memory cells correspondingly; one of the word lines is electrically connected with one of the columns of memory cells; the second end of each first switch module is electrically connected with at least one word line, and the second end of each second switch module is correspondingly electrically connected with at least one word line.
16. 16. An electronic device comprising a memory as claimed in claim 15 or a circuit arrangement as claimed in any of claims 1-14.
17. 17. A data read-write method applied to the circuit structure according to any one of claims 1 to 14, the method comprising: In the activation stage, for the selected word line, the first end and the second end of the corresponding first switch module are controlled to be conducted, the first end and the second end of the corresponding second switch module are controlled to be disconnected, and the first control voltage is applied to the corresponding second control signal line, so that the target memory cell corresponding to the word line is shared with the bit line charge, and data reading and writing are performed.
18. 18. The method of claim 17, further comprising, before the activation phase and/or after the activation phase: In a precharge stage, the first end and the second end of each first switch module are controlled to be disconnected, the first end and the second end of each second switch module are controlled to be conducted, and each fourth control signal line applies a second control voltage so that a memory device of the target memory cell is disconnected from a bit line; One of the first control voltage and the second control voltage is at a high level, and the other is at a low level.

Description

Circuit structure, data reading and writing method, memory and electronic equipment Technical Field The application relates to the technical field of semiconductors, in particular to a circuit structure, a data reading and writing method, a memory and electronic equipment. Background With the increasing demand of storage density, the development of traditional two-dimensional storage architecture is more difficult, and the three-dimensional architecture is further turned to. The more complex interconnection and control of three-dimensional architecture makes it difficult to build with respect to performance and manufacturing. Charge sharing of memory cells and bit lines in a memory requires gating of corresponding Word Lines (WL) to control the turn-on of switching devices of the memory cells. However, the conventional word line gating has problems of more control signals and more troublesome control. Disclosure of Invention Aiming at the defects of the prior art, the application provides a circuit structure, a data read-write method, a memory and electronic equipment, which are used for solving the technical problems that the prior word line gating needs more control signals and is troublesome to control. In a first aspect, an embodiment of the present application provides a circuit structure, including at least one group of switch units, each group of switch units including at least two first switch modules and at least two second switch modules; the control end and the first end of each first switch module are respectively and correspondingly electrically connected with a first control signal line and a second control signal line, and the second end of each first switch module is used for being electrically connected with at least one word line; The control end and the first end of each second switch module are respectively and correspondingly electrically connected with a third control signal line and a fourth control signal line, and the second end of each second switch module is used for being correspondingly and electrically connected with at least one word line; The first ends of the at least two first switch modules arranged along the first direction are correspondingly and electrically connected with the same second control signal line; In each group of switch units, the control ends of at least two first switch modules arranged along the second direction are correspondingly and electrically connected with the same first control signal line, and the control ends of at least two second switch modules arranged along the second direction are correspondingly and electrically connected with the same third control signal line; The circuit structure is used for conducting the first end and the second end of the corresponding first switch module, disconnecting the first end and the second end of the corresponding second switch module and applying the first control voltage to the corresponding second control signal line in the activation stage aiming at the selected word line, so that the target memory cell corresponding to the word line is shared with the bit line charge, and data reading and writing are performed. In one possible implementation, the circuit structure is configured to disconnect the first terminal and the second terminal of each first switch module, and to connect the first terminal and the second terminal of each second switch module, and to apply the second control voltage to each fourth control signal line during the precharge phase, so that the memory device of the memory cell is electrically disconnected from the bit line; Wherein one of the first control voltage and the second control voltage is at a high level and one of the first control voltage and the second control voltage is at a low level, and the precharge phase is located before and/or after the activation phase. In one possible implementation, the first ends of a row of first switch modules arranged along the first direction are correspondingly electrically connected with the same second control signal line; the control ends of a group of first switch modules arranged along the second direction are correspondingly and electrically connected with the same first control signal line, and the control ends of a group of second switch modules arranged along the second direction are correspondingly and electrically connected with the same third control signal line. In one possible implementation, the first switch module includes a first switch device, a gate of the first switch device being a control terminal of the first switch module, one of a source and a drain of the first switch device being a first terminal of the first switch module, the other being a second terminal of the first switch module; The second switch module comprises a second switch device, wherein a grid electrode of the second switch device is used as a control end of the second switch module, and one of a source electrode and a drain electrode of the second