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CN-122024783-A - 4T2MTJ memory cell and memory calculation method thereof

CN122024783ACN 122024783 ACN122024783 ACN 122024783ACN-122024783-A

Abstract

The first aspect of the invention discloses a 4T2MTJ memory cell based on a STT assisted SOT field-free write mechanism. The second aspect of the invention discloses an in-memory computing method of the 4T2MTJ memory cell. Compared with the traditional 2T1MTJ MRAM structure, the SRAM structure needs a plurality of auxiliary CMOS circuits and reference paths to realize basic logic operation, has low area utilization rate and limited logic expansion, has quick reading characteristics, but has low storage density, high power consumption and no nonvolatile property. According to the invention, the functions of a full adder and the like are realized in a single MRAM memory cell (4T 2 MTJ) for the first time, a novel MRAM memory-computing unit with high density, low energy consumption, low delay and strong logic function is successfully constructed through a cooperative switching mechanism of a differential 4T2MTJ structure and STT/SOT, and a powerful foundation is provided for constructing an in-memory computing chip architecture with high energy efficiency and high performance.

Inventors

  • ZHU ZHIFENG
  • XU ZHENGDE

Assignees

  • 上海科技大学

Dates

Publication Date
20260512
Application Date
20260112

Claims (7)

  1. 1. A4T 2MTJ memory cell is characterized by comprising four transistors and two magnetic tunnel junctions, wherein the four transistors are respectively a first transistor, a second transistor, a third transistor, a fourth transistor, a first magnetic tunnel junction and a second magnetic tunnel junction, the first magnetic tunnel junction and the second magnetic tunnel junction share a heavy metal layer, the heavy metal layer is simultaneously used as a spin orbit torque writing path, the first transistor, the second transistor, the third transistor and the fourth transistor are respectively controlled by word lines, the first magnetic tunnel junction is connected with a source line and a bit line through the first transistor and the second transistor, the read-out path of the first magnetic tunnel junction is controlled by the first transistor and the second transistor, the magnetic tunnel junction is connected with the source line and the second bit line through the third transistor and the fourth transistor, and the read-out path of the second magnetic tunnel junction is controlled by the third transistor and the fourth transistor.
  2. 2. The 4T2MTJ memory cell of claim 1 wherein the resistance states of the first and second magnetic tunnel junctions correspond to stored "1" and "0" logic states, wherein the resistance states are low or high resistance states formed in parallel or antiparallel.
  3. 3. The 4T2MTJ memory cell of claim 1, wherein a precharge-evaluate two-stage read scheme is employed to improve read sensitivity, support millivolt voltage resolution, and perform hybrid circuit simulation verification on a 45nm CMOS process platform to ensure logic functional correctness and circuit timing stability.
  4. 4. A method for calculating the memory of 4T2MTJ memory unit as defined in claim 1, wherein during writing, a transverse pulse current is injected into an overweight metal layer to generate spin orbit moment, and simultaneously a small-amplitude spin transfer moment is applied in an auxiliary mode to drive the magnetization directions of a first free layer and a second free layer of the magnetic tunnel junction to turn over, during reading operation, when a control transistor corresponding to a target magnetic tunnel junction is triggered, a small-amplitude reading current is injected into the target magnetic tunnel junction, a voltage difference is generated between the resistance state and a reference branch circuit of the target magnetic tunnel junction, the voltage difference is amplified and judged, a current detection mechanism is introduced into a reading path, in-situ logic operation is realized through the difference of serial combination states of the magnetic tunnel junctions, the method comprises the steps of utilizing resistance state codes of the first magnetic tunnel junction and the second magnetic tunnel junction, wherein the low resistance state is logic '1', the high resistance state is logic '0', a serial reading structure is constructed, a plurality of reference resistances are arranged, the reading current values are compared, a basic logic gate structure is realized, and the method is further expanded into a full-adder structure through three-unit combination, and the fusion of operation and storage is realized.
  5. 5. The method of claim 4, wherein the writing process comprises a first step of injecting a transverse current through the heavy metal layer to excite spin-orbit torque in the in-plane direction, and simultaneously applying a short pulse spin-transfer torque current through the first magnetic tunnel junction and the second magnetic tunnel junction to rotate the magnetization of the free layer from +z direction to the in-plane direction under the combined action of the two, and a second step of applying the rest spin-transfer torque pulse continuously after the spin-orbit torque pulse is ended to stably drive the magnetization of the free layer to rotate in the-z direction to realize deterministic switching to the high-resistance state.
  6. 6. The method of claim 4, wherein for NOR operation, the series reference resistance is set to high resistance, the logic "1" is determined to be "0" only when all magnetic tunnel junctions are in high resistance state, the series reference resistance is set to low resistance when the magnetic tunnel junctions are read, the logic "1" is determined to be high when any magnetic tunnel junction is in high resistance state, and the inversion logic is implemented by the complementary design of the read circuits of the first and second magnetic tunnel junctions.
  7. 7. The method of claim 4, wherein the majority logic expression is MAJ3 (A, B, C) =AB+BC+AC=AB+ (A+B) C, wherein when C=1, the threshold resistance is selected to be high, the threshold setting is such that "1" is output only when A=B=0, NOR logic is completed, the read circuit complementary output is "0" AND OR logic is completed, wherein operands A AND B are determined by the first AND second states of the magnetic tunnel junction AND are both in the high resistance state, AND when C=0, the threshold resistance is selected to be low, the threshold setting is such that "1" is output when either A OR B is in the high resistance state, NAND logic is completed, AND the complementary output is "0", AND AND logic is completed.

Description

4T2MTJ memory cell and memory calculation method thereof Technical Field The invention relates to a magnetic random access Memory (Magnetic Random Access Memory, MRAM) cell structure and a read-write method suitable for an on-chip cache (on-CHIP CACHE) environment, and simultaneously relates to a magnetic Memory circuit design, an integrated circuit manufacture, a low-power consumption computing architecture and a novel logic operation mechanism, belonging to the technical field of nonvolatile memories (NVM) and computing-in-Memory (CiM), and being the cross technical field of embedded Memory and Memory computing fusion in integrated circuits, magnetic devices and artificial intelligent chips. Background With the rapid development of applications such as artificial intelligence (ARTIFICIAL INTELLIGENCE, AI), internet of things (Internet of Things, ioT), and high-performance computing (High Performance Computing, HPC), chip systems face increasingly stringent challenges in terms of power consumption, bandwidth, and real-time. In a traditional "von neumann" architecture, the processor is physically separated from the memory, resulting in a large amount of data being frequently transferred between the two, creating a significant performance bottleneck, also known as a "memory wall" or "bandwidth wall". Especially, when executing massive parallel computing tasks represented by addition, multiplication and the like, time delay and energy consumption cost caused by data movement become key factors for limiting the improvement of the overall performance of the system. For the bottlenecks described above, in-Memory-storage (CiM) technologies have evolved. CiM realizes data 'in-situ processing' by integrating computing capacity in a storage unit, thereby remarkably reducing delay and energy consumption expense caused by data movement and improving computing efficiency. Among the various memory technologies, magnetoresistive Random Access Memory (MRAM) is the first choice for a high-efficiency CiM solution due to its non-volatility, high-speed read and write, excellent endurance, and good CMOS compatibility. In recent years, regarding the logic computing capability of MRAM, students at home and abroad propose various innovative ways to realize but mostly rely on complex circuit structures or device structures. In addition, conventional STT-MRAM devices typically rely on an externally applied magnetic field or a current polarity reversal to achieve writing, resulting in high write current density, large power consumption, and limited device lifetime, which is difficult to accommodate for large scale integration and high reliability requirements. To break through the above limitations, spin-Orbit Torque (SOT) technology is increasingly being introduced into MRAM designs. SOT is based on spin Hall effect in heavy metal and ferromagnetic material heterojunction, realizes that under the unchangeable condition of perpendicular current path, through transversely injecting electric current production moment, effectively realizes writing and reading path separation, improves the write-in reliability and reduces critical current density. The synergy of Spin-Transfer Torque (STT) and SOT not only can remarkably reduce the writing energy consumption, but also can improve the writing certainty and reduce the error writing probability. However, most of the SOT-MRAM schemes still have difficulty in combining high-density integration with low-cost on-chip cache requirements, and have insufficient compatibility with the conventional SRAM structure, so that popularization and application of the SOT-MRAM in actual chip cache design are limited. In view of the above, the prior art still has significant shortcomings in several key aspects: 1. The existing memory computing unit based on the MRAM generally depends on the structural design of a complex memory unit or needs to be matched with a complex peripheral circuit to realize the computing function, so that the overall design area is increased, the manufacturing cost and the design complexity are obviously improved, and the large-scale integration and the application popularization are not facilitated; 2. MRAM devices employing a single STT or single SOT write mechanism are difficult to balance between low power consumption, write certainty, and high device reliability, and write current density is high and write speed is limited, limiting their practicality in high performance in-memory computation; 3. In the existing MRAM in-memory computing design, multiple units are usually required to cooperate or operate in multiple steps to complete complex boolean logic functions such as Majority selector (Majority Gate), adder, etc., and it is difficult for a single memory unit to efficiently implement complex logic operation, which affects operation efficiency and circuit simplicity. Therefore, there is a need for an MRAM memory cell with compact structure, supporting separation of read and w