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CN-122024785-A - Low-temperature SF-eDRAM and low-temperature self-adaptive reference voltage generation circuit

CN122024785ACN 122024785 ACN122024785 ACN 122024785ACN-122024785-A

Abstract

The first aspect of the present invention discloses a low temperature SF-eDRAM, which is characterized by comprising a write pipe N1, a read pipe P1, a gate pipe N2, a gate pipe P2, and a capacitor C 0 . The second aspect of the technical scheme of the invention discloses a low-temperature self-adaptive reference voltage generating circuit. Aiming at the problems of large memory cell area and limited density in the traditional SRAM-based ACAM design, the invention provides a novel eDRAM-based architecture, which remarkably improves the memory density by optimizing the memory cell structure, a reference voltage generating circuit and a reading circuit, and simultaneously supports bidirectional ACAM searching, in-memory logic operation and matrix transposition. The technology disclosed by the invention is suitable for data-intensive applications such as artificial intelligent accelerators, network routers and the like which can be arranged in a low-temperature environment and need efficient parallel search and near-memory computation.

Inventors

  • HA YAJUN
  • WANG JINCHENG

Assignees

  • 上海科技大学

Dates

Publication Date
20260512
Application Date
20260121

Claims (8)

  1. 1. The low-temperature SF-eDRAM is characterized by comprising a write tube N1, a read tube P1, a gate tube N2, a gate tube P2 and a capacitor C 0 , wherein a source electrode of the write tube N1 is connected with a bit line WBL, a grid electrode of the write tube N1 is connected with a write word line WWL, a drain electrode of the write tube N1 is connected with a storage node SN, the storage node SN is connected with a grounded capacitor C 0 , a grid electrode of the read tube P1, a grid electrode of the gate tube P2 and a grid electrode of the gate tube N2, a drain electrode and a source electrode of the gate tube N2 are respectively connected with a read word line RWL and a read bit line RBL, a drain electrode and a source electrode of the gate tube P2 are respectively connected with a PML signal end and a PSWL signal end, and a drain electrode and a source electrode of the gate tube N2 are respectively connected with an NML signal end and an NSWL signal end.
  2. 2. The SF-eDRAM of claim 1, wherein during the write phase, the write tube N1 is turned on by activating the write word line WWL, the data on the bit line WBL being transferred to the storage node SN maintained by the capacitor C 0 , wherein the storage node SN is stored high when writing a "1" and low when writing a "0".
  3. 3. The SF-eDRAM of claim 2, wherein during the read phase, the read word line RWL is activated, the read tube P1 is turned off if the storage node SN is high, the charge state of the read bit line RBL is not changed to be kept low, and the read tube P1 is turned on if the storage node SN is low, the read bit line RBL is charged to high.
  4. 4. The low temperature SF-eDRAM of claim 1, wherein said gate N2 and said gate P2 are dedicated to search operations, wherein said gate N2 is turned on when said storage node SN is high, said gate P2 is turned off, and wherein said gate P2 is turned on and said gate N2 is turned off when said storage node SN is low.
  5. 5. The low temperature SF-eDRAM of claim 1, wherein each cycle performs a precharge operation on the PML signal terminal or the NML signal terminal, respectively, wherein the PSWL signal terminal and the NSWL signal terminal are connected to the same signal when a search operation is performed, if the PSWL signal terminal or the NSWL signal terminal is "1", if the storage node SN is low, the PML signal terminal is charged to high level while the NML signal terminal is unchanged, if the PSWL signal terminal or the NSWL signal terminal is "0", if the storage node SN is high, the NML signal terminal is leaked to low level while the PML signal terminal is kept unchanged, if the PSWL signal terminal or the NSWL signal terminal is "1", and the storage node is high, or if the PSWL signal terminal or the NSWL signal terminal is "0", and the storage node SN is low, the PML signal terminal is kept charged to low.
  6. 6. The low-temperature self-adaptive reference voltage generating circuit is characterized by comprising 4N replication columns, wherein N is an integer not smaller than 1, each replication column comprises a plurality of low-temperature SF-eDRAMs as claimed in claim 1, NSWL signal ends and PSWL signal ends in each low-temperature SF-eDRAM are named as replica NSWL signal ends and replica PSWL signal ends, and NML signal ends and PML signal ends in each low-temperature SF-eDRAM are named as replica NML signal ends and replica PML signal ends; And for each set of the replication columns, controlling the number of the replica NSWL signal ends and the replica PSWL signal ends of the first replication column and the second replication column to be 1, controlling the number of the replica NSWL signal ends and the replica PSWL signal ends of the third replication column and the replica NSWL signal ends and the replica PSWL signal ends of the fourth replication column to be 0, activating a comparison path of the gate pipe N2 only in the first replication column and the second replication column, transmitting the replica NSWL signal on the replica NSWL signal ends to the replica NML signal ends to generate a reference voltage, and generating a replica signal 3525 only in the third replication column and the fourth replication column, wherein the replica NSWL signal ends and the replica PSWL signal ends of the first replication column and the second replication column are controlled to be 1.
  7. 7. The low-temperature adaptive reference voltage generating circuit as recited in claim 6, wherein in a group of said replica columns, all of said replica NML signal terminals of said first replica column or said second replica column are connected to drain of P-type VCT, source of P-type VCT is grounded, gate voltage V leak is connected to gate, all of said replica PML signal terminals of said third replica column or said fourth replica column are connected to drain of N-type VCT, source of N-type VCT is grounded, and gate voltage V charge is connected to gate.
  8. 8. The low temperature adaptive reference voltage generating circuit according to claim 6, wherein said gate voltage V leak and said gate voltage V charge regulate current intensity by external control.

Description

Low-temperature SF-eDRAM and low-temperature self-adaptive reference voltage generation circuit Technical Field The invention relates to a low-temperature embedded dynamic random access Memory (embedded dynamic random access Memory, eDRAM) macro unit based on a 4T1C (4 transistor 1 capacitor, 4T 1C) structure, which is used for approximately searching content addressable Memory (Approximately Content-addressable Memory, ACAM) and in-Memory Logic (LiM) operations. The invention also relates to a low-temperature self-adaptive reference voltage generation circuit based on the low-temperature embedded dynamic random access memory macro unit. The technical scheme disclosed by the invention belongs to the field of integrated circuit design. Background Similar search content addressable memory (ACAM) is widely used in the field of high performance computing because of its parallel search capability, eDRAM can realize high density, but has a problem that leakage current is significantly increased at room temperature and advanced process nodes, resulting in a reduction in data retention time. In addition, as word length increases, the spacing between adjacent hamming distance tolerance levels continues to shrink, making the design more susceptible to noise and leakage currents. Although having advantages of reducing thermal noise and suppressing leakage current in a low temperature environment (documents [1], [2], [3], [4], [5], [6 ]), the implementation of ACAM still needs to solve several problems as follows: 1. The circuit design needs to avoid excessive area overhead, document [7]; 2. The small voltage spacing between adjacent hamming distance tolerance levels amplifies the effects of noise and ripple, so on-chip adaptive reference voltage generation circuitry must be integrated, eliminating the need for off-chip calibration and bi-directional signal communication, literature [8]; Third, at high hamming distance tolerance levels, the accumulated mismatch may shift the ML voltage to a level below the NMOS threshold voltage (or above the PMOS threshold voltage), resulting in a transistor that does not operate efficiently, limiting the hamming distance tolerance range achievable with conventional Sense Amplifiers (SA) [5], [9]. Reference to the literature [1] E. Garz´on, Y. Greenblatt, O. Harel, M. Lanuzza, and A. Teman, "Gain-Cell Embedded DRAM Under Cryogenic Operation—A First Study,"IEEE Transactions on Very Large Scale Integration (VLSI) Systems,vol. 29, no. 7, pp. 1319–1324, 2021. [2] Z. Tang, Z. Wang, Y. Yuan, C. He, X. Luo, A. Guo, R. Chen, Y. Hu, L. Yang, C. Cao, L. Lin Liu, L. Yu, G. Shang, Y. Cao, S. Chen, Y. Zhao, S. Hu, and X. Kou, "Generic Cryogenic CMOS Device Modeling and EDA-Compatible Platform for Reliable Cryogenic IC Design," IEEE Journal of the Electron Devices Society, vol. 13, pp. 117–127, 2025. [3] C. He, Y. Xin, L. Yang, Z. Wang, Z. Tang, X. Luo, R. Chen, Z. Wang, S. Kong, J. Wang et al., "Optimized Cryo-CMOS Technology with VTH ＜ 0.2 V and Ion ＞ 1.2 mA/um for High-Peformance Computing," arXiv preprint arXiv:2411.03099, 2024. [4] J. Wang, J. He, M.-K. Law, X. Wang, F. Liang, and L. Cheng, "A 76.9 ppm/K Nano-Watt PVT-Insensitive CMOS Voltage Reference Operating From 4 to 300 K for Integrated Cryogenic Quantum Interface," IEEE Journal of Solid-State Circuits, vol. 60, no. 9, pp. 3242–3256, 2025. [5] Y. Shu, H. Zhang, Q. Deng, H. Sun, Z. Lv, Y. Li, and Y. Ha, "eCIMC: A 603.1-TOPS/W eDRAM-Based Cryogenic In-Memory Computing Accelerator Supporting Boolean/Convolutional Operations," IEEE Journal of Solid-State Circuits, vol. 59, no. 11, pp. 3827–3839, 2024. [6] Y. Shu, H. Zhang, Q. Deng, H. Sun, and Y. Ha, "CIMC: A 603TOPS/W In-Memory-Computing C3T Macro with Boolean/Convolutional Operation for Cryogenic Computing," in 2023 IEEE Custom Integrated Circuits Conference (CICC), 2023, pp. 1–2. [7] R. Hanhan, E. Garz´on, Z. Jahshan, A. Teman, M. Lanuzza, and L. Yavits, "EDAM: edit distance tolerant approximate matching content addressable memory," in Proceedings of the 49th Annual International Symposium on Computer Architecture, ser. ISCA '22. New York, NY, USA: Association for Computing Machinery, 2022, p. 495–507. [8]E. Garz´on, E. Rechef, R. Golman, O. Harel, Y. Harary, P. Snapir, M. Lanuzza, A. Teman, and L. Yavits, "A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance," IEEE Journal of Solid-State Circuits, pp. 1–11, 2025. [9] Z. Lin, Z. Zhu, H. Zhan, C. Peng, X. Wu, Y. Yao, J. Niu, and J. Chen, "Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports," IEEE Journal of Solid-State Circuits, vol. 56, no. 9, pp. 2832–2844, 2021.S. Xie, S. R. S. Raman, C. Ni, M. Wang, M. Yang, and J. P. Kulkarni. [10]"Ising-CIM: A Reconfigurable and Scalable Compute Within Memory Analog Ising Accelerator for Solving Combinatorial Optimization Problems," IEEE Journal of Solid-State Circuits, vol. 57, no. 11, pp. 34533465, 202