CN-122024786-A - Quick low leakage SRAM cell

Abstract

Disclosed herein are fast low leakage SRAM cells, for example, for digital display systems. In one embodiment, a bit storage circuit includes a latch coupled between a supply voltage and ground, and first through fourth transistors. The latch may include a pair of cross-coupled inverters having a first inverter and a second inverter. The first transistor may selectively couple the first inverter to the supply voltage based at least in part on a first control signal. The second transistor may selectively couple an input of the first inverter to ground based at least in part on a second control signal different from the first control signal. The third transistor may selectively couple the second inverter to the supply voltage based at least in part on the second control signal. The fourth transistor may selectively couple an input of the second inverter to ground based at least in part on the first control signal.

Inventors

• YI JINGJUN
• QIN QING
• DAI TIEJUN
• WU RIXIN

Assignees

• 豪威科技股份有限公司

Dates

Publication Date

20260512

Application Date

20250911

Priority Date

20241111

Claims (20)

1. 1. A bit storage circuit, comprising: A latch coupled between a supply voltage and ground, the latch comprising a pair of cross-coupled inverters having a first inverter and a second inverter; A first transistor coupled between the first inverter and the supply voltage, the first transistor configured to selectively couple the first inverter to the supply voltage based at least in part on a first control signal; a second transistor coupled between an input of the first inverter and ground, the second transistor configured to selectively couple the input of the first inverter to ground based at least in part on a second control signal different from the first control signal; A third transistor coupled between the second inverter and the supply voltage, the third transistor configured to selectively couple the second inverter to the supply voltage based at least in part on the second control signal, and A fourth transistor coupled between an input of the second inverter and ground, the fourth transistor configured to selectively couple the input of the second inverter to ground based at least in part on the first control signal.
2. 2. The bit storage circuit of claim 1, further comprising a diode, wherein the diode and the first transistor are coupled in parallel between the first inverter and the supply voltage.
3. 3. The bit storage circuit of claim 2, wherein the diode comprises a PMOS transistor having (i) a source terminal, (ii) a drain terminal, and (iii) a gate coupled to the drain terminal.
4. 4. The bit storage circuit of claim 2, wherein the diode includes a low threshold or high leakage transistor.
5. 5. The bit storage circuit of claim 2, wherein the diode includes a transistor having a length less than the first transistor.
6. 6. The bit storage circuit of claim 2, wherein the diode includes a transistor having a threshold voltage lower than a threshold voltage of the first transistor.
7. 7. The bit storage circuit of claim 2, wherein the diode is a first diode, wherein the bit storage circuit further comprises a second diode, and wherein the second diode and the third transistor are coupled in parallel between the second inverter and the supply voltage.
8. 8. The bit storage circuit of claim 1, further comprising a fifth transistor, wherein the fifth transistor and the first transistor are coupled in parallel between the first inverter and the supply voltage.
9. 9. The bit storage circuit of claim 8, wherein the fifth transistor includes a gate coupled to receive a bias voltage.
10. 10. The bit storage circuit of claim 9, wherein the fifth transistor is configured to conduct a current between the supply voltage and the first inverter that is greater than a leakage current from the first inverter upon receiving the bias voltage at the gate.
11. 11. The bit storage circuit of claim 10, wherein the current is approximately 20nA.
12. 12. The bit storage circuit of claim 8, further comprising a sixth transistor, wherein the sixth transistor and the third transistor are coupled in parallel between the second inverter and the supply voltage, and wherein the sixth transistor includes a gate coupled to receive a bias voltage.
13. 13. The bit storage circuit of claim 1, wherein: the first inverter includes a fifth transistor and a sixth transistor; The fifth transistor includes a source coupled to the first transistor and either (a) a diode or (b) a transistor having a gate coupled to receive a bias voltage, a gate coupled to the input of the first inverter, and a drain coupled to an output of the first inverter; the diode or the transistor and the first transistor are coupled in parallel between the power supply voltage and the first inverter, and The sixth transistor includes a drain coupled to the drain of the fifth transistor and the output of the first inverter, a source coupled to ground, and a gate coupled to the input of the first inverter.
14. 14. The bit storage circuit of claim 13, wherein: the second inverter includes a seventh transistor and an eighth transistor; The seventh transistor includes a source coupled to the third transistor and to (a) another diode or (b) another transistor having a gate coupled to receive the bias voltage, a gate coupled to the input of the second inverter, and a drain coupled to an output of the second inverter; the other diode or the other transistor and the third transistor are coupled in parallel between the power supply voltage and the second inverter, and The eighth transistor includes a drain coupled to the drain of the seventh transistor and the output of the second inverter, a source coupled to ground, and a gate coupled to the input of the second inverter.
15. 15. The bit storage circuit of claim 1, further comprising a fifth transistor coupled between the second transistor and the input of the first inverter, the fifth transistor configured to selectively couple the second transistor to the input of the first inverter based at least in part on a third control signal different from the first control signal and the second control signal.
16. 16. The bit storage circuit of claim 15, further comprising a sixth transistor coupled between the fourth transistor and the input of the second inverter, the sixth transistor configured to selectively couple the fourth transistor to the input of the second inverter based at least in part on the third control signal.
17. 17. The bit storage circuit of claim 15, wherein the first control signal is a set control signal, the second control signal is a clear control signal, and the third control signal is a word line select control signal.
18. 18. The bit storage circuit of claim 1, wherein the bit storage circuit comprises a static random access memory cell.
19. 19. A bit storage circuit, comprising: A first inverter; a second inverter having (i) an input coupled to an output of the first inverter, and (ii) an output coupled to an input of the first inverter; A first transistor configured to selectively couple the first inverter to a supply voltage; A second transistor configured to selectively couple the first inverter to ground; a third transistor configured to selectively couple the first inverter to the second transistor; a fourth transistor configured to selectively couple the second inverter to the supply voltage; a fifth transistor configured to selectively couple the second inverter to ground, and A sixth transistor configured to selectively couple the second inverter to the fifth transistor.
20. 20. The bit storage circuit of claim 19, further comprising a diode, wherein the diode and the first transistor are coupled in parallel between the supply voltage and the first inverter.

Description

Quick low leakage SRAM cell Technical Field The present disclosure relates generally to bit storage devices and associated devices, systems, and methods. For example, several embodiments described in detail below relate to fast, low leakage Static Random Access Memory (SRAM) cells, such as for digital displays and/or display pixel circuitry. Background SRAM cells are an essential component in digital displays that provide a fast and reliable way of storing pixel data. Each SRAM cell typically includes a transistor configured to hold a single bit of data and directly control the state of the corresponding pixel. In digital displays such as LCDs and OLEDs, SRAM cells are used to maintain the on or off state of individual pixels, ensuring that the correct image or video frame is displayed. Unlike Dynamic RAM (DRAM), SRAM does not need to be constantly refreshed, making it well suited for applications where fast access to stored data and stability are critical, especially in high performance graphics or real-time image processing. SRAM cells are valued for their low latency data retrieval and high speed, enabling the display to reproduce images smoothly and without delay. These characteristics make the SRAM cell a preferred choice for devices requiring fast response times, such as smartphones, tablet computers, and high resolution monitors. The stable storage capability of the SRAM cell helps to ensure consistent pixel performance, thereby improving the overall quality of the digital display. Disclosure of Invention In an example, a bit storage circuit is described. The bit storage circuit includes a latch coupled between a supply voltage and ground, wherein the latch includes a pair of cross-coupled inverters having a first inverter and a second inverter, a first transistor coupled between the first inverter and the supply voltage, a second transistor coupled between an input of the first inverter and ground, a third transistor coupled between the second inverter and the supply voltage, and a fourth transistor coupled between an input of the second inverter and ground. The first transistor is configured to selectively couple the first inverter to the supply voltage based at least in part on a first control signal, the second transistor is configured to selectively couple the input of the first inverter to ground based at least in part on a second control signal different from the first control signal, the third transistor is configured to selectively couple the second inverter to the supply voltage based at least in part on the second control signal, and the fourth transistor is configured to selectively couple the input of the second inverter to ground based at least in part on the first control signal. In an example, a bit storage circuit is described. The bit storage circuit includes a first inverter, a second inverter having (i) an input coupled to an output of the first inverter, and (ii) an output coupled to an input of the first inverter, a first transistor configured to selectively couple the first inverter to a supply voltage, a second transistor configured to selectively couple the first inverter to ground, a third transistor configured to selectively couple the first inverter to the second transistor, a fourth transistor configured to selectively couple the second inverter to the supply voltage, a fifth transistor configured to selectively couple the second inverter to ground, and a sixth transistor configured to selectively couple the second inverter to the fifth transistor. In an example, a method is described. The method includes writing to a latch of a bit storage circuit. Writing the latch includes selectively coupling an input of a first inverter of the latch and an output of a second inverter of the latch to ground such that the input of the first inverter and the output of the second inverter are pulled down toward a first voltage, and cutting or weakening a pull-up leg of the second inverter at least when the input of the first inverter is selectively coupled to ground, wherein the pull-up leg of the second inverter extends between a supply voltage and the second inverter. Drawings Non-limiting and non-exhaustive embodiments of the present technology are described below with reference to the following figures, wherein like or similar reference numerals are used to refer to like or similar components throughout unless otherwise specified. FIG. 1 is a partial schematic diagram of a digital display system configured in accordance with various embodiments of the present technique. FIG. 2 is a schematic diagram of a portion of a display pixel array of the digital display system of FIG. 1. FIG. 3 is a partial schematic diagram of a bit storage circuit configured in accordance with various embodiments of the present technique. FIG. 4 is a partial schematic diagram of another bit storage circuit configured in accordance with various embodiments of the present technique. FIG. 5 is an exemplary timin