CN-122024787-A - Quick low leakage SRAM cell

Abstract

Disclosed herein are fast low leakage SRAM cells, for example, for digital display systems. In one embodiment, a bit storage circuit includes a latch, a first transistor, and a second transistor. The latch may have a pair of cross-coupled inverters including a first inverter and a second inverter. The first transistor may have a source coupled to receive a first control signal, a drain coupled to an input of the first inverter, and a gate coupled to receive a word line select control signal. The second transistor may have a source coupled to receive a second control signal different from the first control signal, a drain coupled to an input of the second inverter, and a gate coupled to receive the word line selection control signal.

Inventors

• YI JINGJUN
• QIN QING
• DAI TIEJUN
• WU RIXIN

Assignees

• 豪威科技股份有限公司

Dates

Publication Date

20260512

Application Date

20250915

Priority Date

20241111

Claims (20)

1. 1. A bit storage circuit, comprising: a latch having a pair of cross-coupled inverters including a first inverter and a second inverter; A first transistor having a source coupled to receive a first control signal, a drain coupled to an input of the first inverter, and a gate coupled to receive a word line select control signal, an A second transistor having a source coupled to receive a second control signal different from the first control signal, a drain coupled to an input of the second inverter, and a gate coupled to receive the word line select control signal.
2. 2. The bit storage circuit of claim 1, wherein: The first inverter includes A third transistor having a source coupled to a supply voltage, a gate coupled to the input of the first inverter, and a drain, an A fourth transistor having a source coupled to ground, a gate coupled to the input of the first inverter, and a drain The bit storage circuit further includes a fifth transistor selectively coupling the drain of the third transistor to the drain of the fourth transistor.
3. 3. The bit storage circuit of claim 2, wherein the fifth transistor includes a source coupled to the drain of the third transistor, a drain coupled to the drain of the fourth transistor, and a gate coupled to receive the first control signal.
4. 4. The bit storage circuit of claim 2, wherein: The second inverter includes A sixth transistor having a source coupled to a supply voltage, a gate coupled to the input of the second inverter, and a drain, an A seventh transistor having a source coupled to ground, a gate coupled to the input of the second inverter, and a drain The bit storage circuit further includes an eighth transistor selectively coupling the drain of the sixth transistor to the drain of the seventh transistor.
5. 5. The bit storage circuit of claim 4, wherein the eighth transistor includes a source coupled to the drain of the sixth transistor, a drain coupled to a drain of the seventh transistor, and a gate coupled to receive the second control signal.
6. 6. The bit storage circuit of claim 4, wherein: the sixth transistor includes a bulk terminal coupled to the supply voltage, and The eighth transistor includes a bulk terminal coupled to the supply voltage.
7. 7. The bit storage circuit of claim 4, wherein: The sixth transistor includes a body terminal selectively couplable to (a) ground based at least in part on a first mode of operation of the bit storage circuit and (b) the power supply voltage based at least in part on a second mode of operation of the bit storage circuit, and The eighth transistor includes a body terminal selectively coupleable to ground based at least in part on the first mode of operation of the bit storage circuit and selectively coupleable to the supply voltage based at least in part on the second mode of operation of the bit storage circuit.
8. 8. The bit storage circuit of claim 7, wherein the first mode of operation is an active mode of the bit storage circuit, and wherein the second mode of operation is a standby or sleep mode of the bit storage circuit.
9. 9. The bit storage circuit of claim 2, wherein: the third transistor includes a body terminal selectively couplable to (a) ground based at least in part on a first mode of operation of the bit storage circuit and (b) the power supply voltage based at least in part on a second mode of operation of the bit storage circuit, and The fifth transistor includes a body terminal selectively coupleable to ground based at least in part on the first mode of operation of the bit storage circuit and selectively coupleable to the supply voltage based at least in part on the second mode of operation of the bit storage circuit.
10. 10. The bit storage circuit of claim 9, wherein the first mode of operation is an active mode of the bit storage circuit, and wherein the second mode of operation is a standby or sleep mode of the bit storage circuit.
11. 11. The bit storage circuit of claim 2, wherein: The third transistor includes a bulk terminal coupled to the supply voltage, and The fifth transistor includes a bulk terminal coupled to the supply voltage.
12. 12. The bit storage circuit of claim 1, wherein a voltage level of the first control signal and/or a voltage level of the second control signal, when asserted, is between about 40% of a voltage level of a supply voltage and about 70% of the voltage level of the supply voltage.
13. 13. A bit storage circuit, comprising: a first inverter having an input, an output, a first transistor and a second transistor, wherein- The first transistor includes a source coupled to a supply voltage, a gate coupled to the input of the first inverter, and a drain, an The second transistor includes a source coupled to ground, a gate coupled to the input of the first inverter, and a drain coupled to the output of the first inverter; A third transistor selectively coupling the drain of the first transistor to the drain of the second transistor based at least in part on a first control signal received at a gate of the third transistor; A second inverter having an input coupled to the output of the first inverter, an output coupled to the input of the first inverter, a fourth transistor, and a fifth transistor, wherein The fourth transistor includes a source coupled to the supply voltage, a gate coupled to the input of the second inverter, and a drain, an The fifth transistor includes a source coupled to ground, a gate coupled to the input of the second inverter, and a drain coupled to the output of the second inverter, and A sixth transistor selectively coupling the drain of the fourth transistor to the drain of the fifth transistor based at least in part on a second control signal received at a gate of the sixth transistor, wherein the second control signal is different from the first control signal.
14. 14. The bit storage circuit of claim 13, further comprising: A seventh transistor selectively coupling a third control signal to the input of the first inverter based at least in part on a write enable signal received at a gate of the seventh transistor, and An eighth transistor selectively coupling a fourth control signal to the input of the second inverter based at least in part on the write enable signal received at a gate of the eighth transistor.
15. 15. The bit storage circuit of claim 14, wherein the third control signal is the first control signal, and wherein the fourth control signal is the second control signal.
16. 16. The bit storage circuit of claim 13, further comprising: a seventh transistor coupled between the input of the first inverter and ground, the seventh transistor including a gate coupled to receive the second control signal; an eighth transistor selectively coupling the seventh transistor to the input of the first inverter based at least in part on a write enable signal received at a gate of the eighth transistor; A ninth transistor coupled between the input of the second inverter and ground, the ninth transistor including a gate coupled to receive the first control signal, and A tenth transistor selectively coupling the ninth transistor to the input of the second inverter based at least in part on the write enable signal received at a gate of the tenth transistor.
17. 17. The bit storage circuit of claim 13, wherein the third transistor and the sixth transistor each include a bulk terminal coupled to the supply voltage.
18. 18. The bit storage circuit of claim 13, wherein: The first transistor includes a body terminal selectively couplable to (a) ground based at least in part on a first mode of operation of the bit storage circuit and (b) the power supply voltage based at least in part on a second mode of operation of the bit storage circuit, and The third transistor includes a bulk terminal selectively coupleable to ground based at least in part on the first mode of operation of the bit storage circuit, and selectively coupleable to the supply voltage based at least in part on the second mode of operation of the bit storage circuit.
19. 19. The bit storage circuit of claim 18, wherein: The fourth transistor includes a body terminal selectively couplable to (a) ground based at least in part on the first mode of operation of the bit storage circuit and (b) the power supply voltage based at least in part on the second mode of operation of the bit storage circuit, and The sixth transistor includes a body terminal selectively coupleable to ground based at least in part on the first mode of operation of the bit storage circuit and selectively coupleable to the supply voltage based at least in part on the second mode of operation of the bit storage circuit.
20. 20. The bit storage circuit of claim 18, wherein the first mode of operation is an active mode of the bit storage circuit, and wherein the second mode of operation is a standby or sleep mode of the bit storage circuit.

Description

Quick low leakage SRAM cell Technical Field The present disclosure relates generally to bit storage devices and associated devices, systems, and methods. For example, several embodiments described in detail below relate to fast, low leakage Static Random Access Memory (SRAM) cells, such as for digital displays and/or display pixel circuitry. Background SRAM cells are an essential component in digital displays that provide a fast and reliable way of storing pixel data. Each SRAM cell typically includes a transistor configured to hold a single bit of data and directly control the state of the corresponding pixel. In digital displays such as LCDs and OLEDs, SRAM cells are used to maintain the on or off state of individual pixels, ensuring that the correct image or video frame is displayed. Unlike Dynamic RAM (DRAM), SRAM does not need to be constantly refreshed, making it well suited for applications where fast access to stored data and stability are critical, especially in high performance graphics or real-time image processing. SRAM cells are valued for their low latency data retrieval and high speed, enabling the display to reproduce images smoothly and without delay. These characteristics make the SRAM cell a preferred choice for devices requiring fast response times, such as smartphones, tablet computers, and high resolution monitors. The stable storage capability of the SRAM cell helps to ensure consistent pixel performance, thereby improving the overall quality of the digital display. Disclosure of Invention In one aspect, the present disclosure is directed to a bit storage circuit comprising a latch having a pair of cross-coupled inverters including a first inverter and a second inverter, a first transistor having a source coupled to receive a first control signal, a drain coupled to an input of the first inverter, and a gate coupled to receive a word line select control signal, and a second transistor having a source coupled to receive a second control signal different from the first control signal, a drain coupled to an input of the second inverter, and a gate coupled to receive the word line select control signal. In another aspect, the present disclosure is directed to a bit storage circuit comprising a first inverter having an input, an output, a first transistor, and a second transistor, wherein-the first transistor includes a source coupled to a supply voltage, a gate coupled to the input of the first inverter, and a drain, and the second transistor includes a source coupled to ground, a gate coupled to the input of the first inverter, and a drain coupled to the output of the first inverter, a third transistor selectively coupling the drain of the first transistor to the drain of the second transistor based at least in part on a first control signal received at the gate of the third transistor, a second inverter having an input coupled to the output of the first inverter, an output coupled to the input of the first inverter, a fourth transistor, and a fifth transistor, wherein-the fourth transistor includes a source coupled to the voltage, a gate coupled to the input of the first inverter, and a drain coupled to the fifth transistor based at least in part on the control signal received at the drain of the second transistor, the fifth transistor being coupled to the input of the fifth inverter, and the fifth transistor. In another aspect, the disclosure relates to a method comprising writing to a latch of a bit storage circuit, wherein the latch includes a pair of cross-coupled inverters, and wherein writing to the latch includes asserting a control signal at a first time, and selectively coupling a voltage level corresponding to the asserted control signal to an input of an inverter of the pair of cross-coupled inverters at a second time that occurs after the first time. Drawings Non-limiting and non-exhaustive embodiments of the present technology are described below with reference to the following figures, wherein like or similar reference numerals are used to refer to like or similar components throughout unless otherwise specified. FIG. 1 is a partial schematic diagram of a digital display system configured in accordance with various embodiments of the present technique. FIG. 2 is a schematic diagram of a portion of a display pixel array of the digital display system of FIG. 1. FIG. 3 is a partial schematic diagram of a bit storage circuit configured in accordance with various embodiments of the present technique. FIG. 4 is a partial schematic diagram of another bit storage circuit configured in accordance with various embodiments of the present technique. FIG. 5 is an exemplary timing diagram of a bit storage circuit in accordance with various embodiments of the present technique. FIG. 6 is a partial schematic diagram of yet another bit storage circuit configured in accordance with various embodiments of the present technique. Skilled artisans will appreciate that elements in the figures ar