CN-122024788-A - Nonvolatile static memory based on floating gate transistor structure

CN122024788ACN 122024788 ACN122024788 ACN 122024788ACN-122024788-A

Abstract

The invention discloses a nonvolatile static memory based on a floating gate transistor structure, relates to the technical field of memories, and is used for solving the problems of easiness in losing a six-tube unit of an SRAM, low Flash operation speed and immature part of memory technology in the prior art. The nonvolatile floating gate memory device at least comprises an SRAM six-tube unit and a nonvolatile floating gate memory device combined with the SRAM six-tube unit, wherein the nonvolatile floating gate memory device comprises two groups of floating gate transistor structures which are arranged in mirror symmetry and are used for carrying out data interaction with the SRAM six-tube unit in different working stages so as to realize nonvolatile memory function. The nonvolatile static memory structure provided by the invention can have the advantages of high speed of the six-tube unit of the SRAM and nonvolatile characteristic of Flash, and improves the performance and reliability of the memory.

Inventors

XIE YUANLU
XU XIAOXIN
Ji Lanlong
DONG DANIAN
HU HONGYANG
WANG YAN
LU NIANDUAN

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260512
Application Date: 20251212

Claims (10)

1.A non-volatile static memory based on a floating gate transistor structure, comprising at least: an SRAM six-tube unit; And a nonvolatile floating gate memory device coupled to the SRAM six-transistor cell; The nonvolatile floating gate memory device comprises two groups of floating gate transistor structures which are arranged in mirror symmetry and are used for carrying out data interaction with the SRAM six-tube unit in different working stages so as to realize nonvolatile memory function.
2. The non-volatile static memory of claim 1, wherein the SRAM six-transistor cell comprises at least two cross-coupled inverters, the two inverters being interconnected to form a stable memory cell.
3. The non-volatile static memory of claim 1, wherein the non-volatile floating gate memory device stores data of the SRAM six-transistor cell prior to power down; The nonvolatile floating gate memory device transmits stored data to the SRAM six-tube unit after being electrified, so that nonvolatile storage of the data is realized; The two groups of floating gate transistor structures simultaneously perform writing operation, so that the driving strength is enhanced.
4. The non-volatile static memory of claim 1, wherein the data on the left and right sides of the SRAM six-tube cell are inverted; The read-write data of the left floating gate transistor structure and the right floating gate transistor structure are in inverse relation, when the left floating gate transistor structure writes 1 into the SRAM six-tube unit, the right floating gate transistor structure writes 0 into the SRAM six-tube unit, and when the left floating gate transistor structure writes 0 into the SRAM six-tube unit, the right floating gate transistor structure writes 1 into the SRAM six-tube unit.
5. The nonvolatile static memory according to claim 1, wherein after power-up, data in the nonvolatile floating gate memory device is read, and the read data is transmitted to the SRAM six-tube cell, so as to complete data initialization of the SRAM six-tube cell; during normal operation, the two groups of floating gate transistor structures are disconnected from the SRAM six-tube unit, and the word line, the left bit line and the right bit line are used for normally reading and writing the SRAM six-tube unit; Before power failure, flash erasing operation is carried out on the nonvolatile floating gate memory device, writing operation is carried out on data in the SRAM six-tube unit, the data in the SRAM six-tube unit are written into two groups of floating gate transistor structures in the nonvolatile floating gate memory device, and nonvolatile storage is carried out.
6. The nonvolatile static memory of claim 5 wherein the Flash erase operation indicates that a predetermined negative voltage is applied to the control gate of the floating gate transistor structure in the nonvolatile floating gate memory device, a predetermined positive voltage is applied to the P-well, and electrons in the floating gate are pulled out of the floating gate, causing the floating gate transistor structure to have a value of all 1.
7. The nonvolatile static memory of claim 5 wherein the write operation is pulling electrons into the floating gate of a floating gate transistor structure based on the level state of a node in the SRAM six-transistor cell, causing the floating gate transistor structure to store corresponding data.
8. The non-volatile static memory of claim 7, wherein during writing data in the SRAM six-transistor cell into two groups of floating gate transistor structures in the non-volatile floating gate memory device, if the QL signal in the SRAM six-transistor cell is high, the QR signal is low, the NL signal is high, the NR signal is low, the number of electrons pulled into the floating gate in the right floating gate transistor structure is greater than the number of electrons pulled into the floating gate in the left floating gate transistor structure, the number of charges in the floating gates of the two groups of floating gate transistor structures is different, resulting in the threshold voltages of the two groups of floating gate transistor structures being different, and completing a data writing operation from the SRAM six-transistor cell to the floating gate transistor structure.
9. The non-volatile static memory of claim 1, wherein the non-volatile floating gate memory device is a ferroelectric memory or a resistive random access memory.
10. The nonvolatile static memory of claim 1 wherein the nonvolatile static memory adaptively adjusts read and write parameters of the nonvolatile floating gate memory device based on the operating state of the SRAM six-transistor cell.

Description

Nonvolatile static memory based on floating gate transistor structure Technical Field The invention relates to the technical field of memories, in particular to a nonvolatile static memory based on a floating gate transistor structure. Background In the technical field of memories, an SRAM six-tube unit (static random access memory) has the advantage of high read-write access speed, but has the problem of data loss after power failure. And the nonvolatile memory, such as NAND FLASH, NOR Flash and the like based on the floating gate transistor structure memory technology, can keep data after power failure, but has slower read-write access speed. The common Flash memory space for storing photo videos in the USB Flash disk, the solid state disk SSD and the mobile phone adopts the memory technology, and in addition, the existing partial memory technology such as the resistive random access memory or the hafnium-based memory technology is still immature. These problems limit the application of memory in scenarios where there is a high demand for data storage speed and non-volatility. Accordingly, there is a need to provide a more reliable nonvolatile static memory based on floating gate transistor structures. Disclosure of Invention The invention aims to provide a nonvolatile static memory based on a floating gate transistor structure, which is used for solving the problems of volatile SRAM six-tube units, low Flash operation speed and immature part of memory technology in the prior art. In order to achieve the above object, the present invention provides the following technical solutions: In a first aspect, the present invention provides a nonvolatile static memory based on a floating gate transistor structure, comprising at least: an SRAM six-tube unit; And a nonvolatile floating gate memory device coupled to the SRAM six-transistor cell; The nonvolatile floating gate memory device comprises two groups of floating gate transistor structures which are arranged in mirror symmetry and are used for carrying out data interaction with the SRAM six-tube unit in different working stages so as to realize nonvolatile memory function. Optionally, the SRAM six-tube unit at least comprises two cross-coupled inverters, and the two inverters are connected with each other to form a stable storage unit. Optionally, the nonvolatile floating gate memory device stores data of the SRAM six-tube cell before power failure; The nonvolatile floating gate memory device transmits stored data to the SRAM six-tube unit after being electrified, so that nonvolatile storage of the data is realized; The two groups of floating gate transistor structures simultaneously perform writing operation, so that the driving strength is enhanced. Optionally, the data on the left side and the right side of the six-tube unit of the SRAM are mutually inverted; The read-write data of the left floating gate transistor structure and the right floating gate transistor structure are in inverse relation, when the left floating gate transistor structure writes 1 into the SRAM six-tube unit, the right floating gate transistor structure writes 0 into the SRAM six-tube unit, and when the left floating gate transistor structure writes 0 into the SRAM six-tube unit, the right floating gate transistor structure writes 1 into the SRAM six-tube unit. Optionally, after power-up, reading data in the nonvolatile floating gate memory device, and transmitting the read data to the SRAM six-tube unit to finish data initialization of the SRAM six-tube unit; during normal operation, the two groups of floating gate transistor structures are disconnected from the SRAM six-tube unit, and the word line, the left bit line and the right bit line are used for normally reading and writing the SRAM six-tube unit; Before power failure, flash erasing operation is carried out on the nonvolatile floating gate memory device, writing operation is carried out on data in the SRAM six-tube unit, the data in the SRAM six-tube unit are written into two groups of floating gate transistor structures in the nonvolatile floating gate memory device, and nonvolatile storage is carried out. Optionally, the Flash erasing operation means that a preset negative voltage is applied to a control gate of a floating gate transistor structure in the nonvolatile floating gate memory device, a preset positive voltage is applied to a P-well, electrons in the floating gate are pulled out of the floating gate, and the numerical value of the floating gate transistor structure is set to be 1. Optionally, the writing operation is to pull electrons into the floating gate of the floating gate transistor structure according to the level state of the node in the six-transistor unit of the SRAM, so that the floating gate transistor structure stores corresponding data. Optionally, in the process of writing the data in the SRAM six-transistor unit into the two groups of floating gate transistor structures in the nonvolatile floati