CN-122024791-A - Semiconductor device, memory device, and electronic apparatus

Abstract

The application provides a semiconductor device, a memory device and electronic equipment, and relates to the technical field of semiconductors. The semiconductor device comprises a storage unit, a first compensation unit and a second compensation unit, wherein the storage unit stores first weight data, the first weight data corresponds to conductance or transconductance of the storage unit, the storage unit is used for being coupled with a first input signal and outputting a first output signal based on the first weight data, the first compensation unit stores second weight data, the second weight data is used for compensating the first weight data, the second weight data corresponds to conductance or transconductance of the first compensation unit, the first compensation unit is used for being coupled with a second input signal and outputting a second output signal based on the second weight data, and the second output signal is used for compensating the first output signal to jointly determine output data of the storage unit. The technical scheme of the application can improve the reliability of the integrated architecture of memory and calculation.

Inventors

• GUO XINJIE

Assignees

• 杭州知存算力科技有限公司

Dates

Publication Date

20260512

Application Date

20241110

Claims (20)

1. 1. A semiconductor device, comprising: A storage unit storing first weight data corresponding to conductance or transconductance of the storage unit, the storage unit is used for coupling a first input signal and outputting a first output signal based on the first weight data; A first compensation unit storing second weight data for compensating the first weight data, the second weight data corresponding to the conductance or transconductance of the first compensation unit, the first compensation unit is used for coupling a second input signal and outputting a second output signal based on the second weight data; The second output signal is used to compensate the first output signal to collectively determine output data of the memory cell.
2. 2. The semiconductor device according to claim 1, wherein the second weight data is determined based on the first weight data and target weight data.
3. 3. The semiconductor device according to claim 2, wherein the second weight data is determined based on a first multiple of a first difference value including an absolute value of a difference between the target weight data and the first weight data.
4. 4. The semiconductor device according to claim 3, wherein the first weight data belongs to a first range, the target weight data belongs to a target range, and the second weight data belongs to a second range; The first difference comprises a first boundary difference comprising an absolute value of a difference between a first boundary value of the target range and a first boundary value of the first range and a second boundary difference comprising an absolute value of a difference between a second boundary value of the target range and a second boundary value of the first range; A first boundary value of the second range is determined based on a first multiple of the first boundary difference value, and a second boundary value of the second range is determined based on the first multiple of the second boundary difference value.
5. 5. The semiconductor device according to claim 3 or 4, wherein the first input signal and the second input signal are the same input signal, and the second output signal is reduced by the first multiple to compensate for the first output signal.
6. 6. The semiconductor device according to claim 5, further comprising: The first conversion unit is connected to the first compensation unit and is used for reducing the second output signal by the first multiple, and the reduced second output signal is used for compensating the first output signal so as to jointly determine the output data of the storage unit.
7. 7. The semiconductor device according to claim 3 or 4, wherein the first input signal is a first multiple of the second input signal.
8. 8. The semiconductor device according to any one of claims 3 to 7, wherein the first multiple is related to one or more of a storage capacity of the first compensation unit, a storage capacity of the storage unit, an effective storage capacity of the storage unit, and a programming accuracy of the storage unit.
9. 9. The semiconductor device according to claim 8, wherein the first multiple is greater than or equal to an effective storage capacity of the memory cell and less than or equal to a storage capacity of the memory cell.
10. 10. The semiconductor device according to any one of claims 1 to 9, characterized in that the semiconductor device further comprises: A second compensation unit storing third weight data for compensating the first weight data together with the second weight data, the third weight data corresponds to the conductance or the transconductance of the second compensation unit, and the second compensation unit is used for coupling a third input signal and outputting a third output signal based on the third weight data; The third output signal and the second output signal are used to compensate the first output signal to jointly determine the output data of the memory cell.
11. 11. The semiconductor device according to claim 10, wherein the third weight data is determined based on the first weight data, the second weight data, and target weight data.
12. 12. The semiconductor device according to claim 11, wherein the third weight data is determined based on a second multiple of a second difference value including an absolute value of a difference of a sum of the second weight data and the first multiple and the first weight data with respect to the target weight data.
13. 13. The semiconductor device according to claim 12, wherein the first input signal, the second input signal, and the third input signal are the same input signal, wherein the first output signal is compensated after the second output signal is scaled down by the first multiple and the third input signal is scaled down by the second multiple.
14. 14. The semiconductor device according to claim 13, further comprising: the first conversion unit is connected with the first compensation unit and is used for reducing the second output signal by the first multiple; and the second conversion unit is connected with the second compensation unit and is used for reducing the third output signal by the second multiple.
15. 15. The semiconductor device according to any one of claims 12 to 14, wherein the second multiple is the same as or different from the first multiple.
16. 16. The semiconductor device according to any one of claims 12 to 15, wherein the second multiple is related to one or more of a storage capacity of the second compensation unit, a storage capacity of the storage unit, an effective storage capacity of the first compensation unit, and a programming accuracy of the storage unit.
17. 17. The semiconductor device according to any one of claims 1 to 16, wherein the semiconductor device includes a memory cell group including N of the memory cells and a first compensation cell group including N of the first compensation cells, N being a positive integer; The N storage units are used for outputting N first output signals in a collinear way, the N first compensation units are used for outputting N second output signals in a collinear way, and the N second output signals are compensated after being reduced by a first multiple X 1 ; The N first output signals and the N reduced second output signals are used for jointly determining operation results of the N storage units.
18. 18. The semiconductor device according to claim 17, wherein N of the memory cells and N of the first compensation cells are located in different memory cell arrays.
19. 19. The semiconductor device according to claim 17 or 18, characterized in that the semiconductor device has a first computational parallelism for determining the number of memory cells comprised by the group of memory cells, and the first computational parallelism is related to an effective memory capacity of a first compensation cell, an effective memory capacity of the memory cells and the first multiple.
20. 20. The semiconductor device according to any one of claims 1 to 19, wherein the memory cell and the first compensation cell comprise the same type of device.

Description

Semiconductor device, memory device, and electronic apparatus Technical Field The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a memory device, and an electronic apparatus. Background In traditional computing modes, such as von neumann architecture, storage and computation are physically separated. When the calculation mode is used for data processing, data is frequently transmitted between the storage device and the calculation device, and data transmission delay and energy consumption are brought. With the development of technologies such as big data and artificial intelligence, the data processing capacity is rapidly increased, and the data transmission requirement is rapidly increased, so that the transmission delay and the energy consumption are increasingly prominent, the development of the data processing capacity is restricted, and the requirement of the processing capacity is difficult to meet in the traditional computing mode. The integrated memory and calculation technology can physically integrate memory and calculation, and the memory device is used for realizing calculation or storing data in the calculation device, so that the data transmission requirement is reduced, the transmission delay and the energy consumption are reduced, and the data processing efficiency is greatly improved. However, the technology of integrating into one remains a challenge, for example, the reliability of the integrated device remains to be improved. Disclosure of Invention The application provides a semiconductor device, a memory device and an electronic device, which are used for improving the reliability of a memory-computing integrated structure. In a first aspect, a semiconductor device is provided, including a memory unit storing first weight data, the first weight data corresponding to a conductance or transconductance of the memory unit, the memory unit being configured to couple to a first input signal and output a first output signal based on the first weight data, a first compensation unit storing second weight data, the second weight data being configured to compensate the first weight data, the second weight data corresponding to a conductance or transconductance of the first compensation unit, the first compensation unit being configured to couple to a second input signal and output a second output signal based on the second weight data, the second output signal being configured to compensate the first output signal to collectively determine output data of the memory unit. According to the technical scheme, the semiconductor device is provided with the additional compensation unit on the basis of the storage unit, the storage error is compensated by the compensation unit, so that the storage error can be compensated in the compensation unit, the programming precision requirement on a single storage unit is reduced, the programming speed is improved, and meanwhile, the integral programming precision is improved by the compensation of the compensation unit, so that the reliability of the integrated architecture is improved. In addition, the introduction of the compensation unit is beneficial to expanding the memory bit width of the memory unit, and under the memory requirement of higher bit width, the programming precision can be improved through the compensation unit, and the programming error is reduced. In addition, the introduction of the compensation unit can also improve the calculation parallelism in the memory calculation scene, which is beneficial to improving the calculation efficiency and further improving the calculation performance of the memory calculation device. With reference to the first aspect, in certain implementations of the first aspect, the second weight data is determined based on the first weight data and the target weight data. In the implementation manner, after the compensation unit is introduced, the first weight data stored in the storage unit can have a certain error relative to the target weight data to be stored, so that the requirement on the programming precision of the storage unit is reduced, the second weight data stored in the compensation unit is utilized to compensate the error, and the programming speed and the programming precision are further improved. Optionally, the second weight data is determined based on a first multiple of a first difference value, the first difference value comprising an absolute value of a difference between the target weight data and the first weight data. According to the technical scheme, the second weight data is set based on the first multiple of the absolute value of the difference between the target weight data and the first weight data, so that the second weight data stored in the compensation unit is larger, the numerical interval span of the second weight data is also larger, the requirement on the programming precision of the compensation unit can b