CN-122024792-A - Double polysilicon non-volatile memory bitcell

Abstract

The present disclosure relates to dual polysilicon non-volatile memory bitcells. A non-volatile memory (NVM) bit cell is disclosed. The NVM bitcell includes a control gate, a state transistor, and an access transistor coupled in series with the state transistor. The control gate includes a floating terminal formed from a first polysilicon layer, a control terminal formed from a second polysilicon layer, and a control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer includes a high-K dielectric layer. The state transistor includes a floating gate terminal formed from a first polysilicon layer and coupled to a floating terminal of the control gate. The state transistor further includes a tunnel oxide layer formed between the first polysilicon layer and an active region of the state transistor.

Inventors

• LIU GANG
• S. Mennong
• A. P. Kosmin
• Bruce Blair Greenwood

Assignees

• 半导体元件工业有限责任公司

Dates

Publication Date

20260512

Application Date

20250320

Priority Date

20241111

Claims (20)

1. 1. A non-volatile memory NVM bitcell, the NVM bitcell comprising: A control gate, the control gate comprising: A floating terminal formed of a first polysilicon layer; a control terminal formed of a second polysilicon layer, and A control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer comprises a high-K dielectric layer; a state transistor, the state transistor comprising: A floating gate terminal formed from the first polysilicon layer and coupled to a floating terminal of the control gate, and A tunnel oxide layer formed between the first polysilicon layer and the active region of the state transistor, and An access transistor coupled in series with the state transistor.
2. 2. The NVM bitcell of claim 1, the NVM bitcell further comprising: A well region in which the state transistor and the access transistor are formed, and A channel region having a channel depth greater than or equal to a well depth of the well region.
3. 3. The NVM bitcell of claim 2, wherein: The well region is a p-well region, and The state transistor and the access transistor are NMOS transistors.
4. 4. The NVM bitcell of claim 2, wherein: the well region is arranged in the deep well, and The well region has a conductivity type opposite to the deep well.
5. 5. The NVM bitcell of claim 1, wherein the state transistor and the control gate are collectively configured to perform erase operations and write operations using Fowler-Nordheim tunneling.
6. 6. The NVM bitcell of claim 1, wherein the control gate dielectric layer further comprises at least one silicon dioxide layer.
7. 7. The NVM bit cell of claim 1, wherein the control gate dielectric layer further comprises a first silicon dioxide layer on a first side of the high-K dielectric layer and a second silicon dioxide layer on a second side of the high-K dielectric layer.
8. 8. An integrated circuit, the integrated circuit comprising: logic block, and A non-volatile memory NVM bitcell array coupled to the logic block, the NVM bitcell array comprising a plurality of NVM bitcells arranged in a plurality of rows and columns, each NVM bitcell comprising: A control gate, the control gate comprising: A floating terminal formed of a first polysilicon layer; a control terminal formed of a second polysilicon layer, and A control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer comprises a high-K dielectric layer; a state transistor, the state transistor comprising: A floating gate terminal formed from the first polysilicon layer and coupled to a floating terminal of the control gate, and A tunnel oxide layer formed between the first polysilicon layer and the active region of the state transistor, and An access transistor coupled in series with the state transistor.
9. 9. The integrated circuit of claim 8, wherein each NVM bitcell further comprises: A well region in which the state transistor and the access transistor are formed, and A channel region having a channel depth greater than or equal to a well depth of the well region.
10. 10. The integrated circuit of claim 9, wherein: The well region is a p-well region, and The state transistor and the access transistor are NMOS transistors.
11. 11. The integrated circuit of claim 9, wherein: the well region is arranged in the deep well, and The well region has a conductivity type opposite to the deep well.
12. 12. The integrated circuit of claim 9, wherein the well region is shared by a first NVM bitcell and one or more adjacent NVM bitcells located in the same column.
13. 13. The integrated circuit of claim 9, wherein the well region of a first NVM bitcell is isolated from the well regions of adjacent NVM bitcells located in the same row by the channel region.
14. 14. The integrated circuit of claim 8, wherein the state transistor and the control gate are collectively configured to perform erase operations and write operations using Fowler-Nordheim tunneling.
15. 15. The integrated circuit of claim 8, wherein the control gate dielectric layer further comprises at least one silicon dioxide layer.
16. 16. The integrated circuit of claim 8, wherein the control gate dielectric layer further comprises a first silicon dioxide layer on a first side of the high-K dielectric layer and a second silicon dioxide layer on a second side of the high-K dielectric layer.
17. 17. A method, the method comprising: Forming a well region; Forming an access transistor in the well region; Forming a state transistor in the well region, the state transistor having a floating gate terminal formed of a first polysilicon layer; A control gate is formed having a floating terminal formed from the first polysilicon layer, a control terminal formed from a second polysilicon layer, and a control gate dielectric layer disposed between the first polysilicon layer and the second polysilicon layer and comprising a high-K dielectric layer.
18. 18. The method of claim 17, further comprising forming a channel region adjoining the well region on at least one side and having a channel depth greater than or equal to a well depth of the well region.
19. 19. The method of claim 17, wherein the control gate dielectric layer is formed with a first silicon dioxide layer on a first side of the high-K dielectric layer and a second silicon dioxide layer on a second side of the high-K dielectric layer.
20. 20. The method of claim 17, wherein the state transistor and the control gate are collectively configured to perform erase operations and write operations using Fowler-Nordheim tunneling.

Description

Double polysilicon non-volatile memory bitcell Technical Field The present disclosure relates generally to integrated circuit technology, and in particular to designs and methods of manufacturing non-volatile memory devices. Background Integrated circuits may be manufactured to include both data processing units (such as central processing units or graphics processing units) and memory blocks that may be used to store data for use by the data processing units. In some configurations, the memory block may include a non-volatile memory (NVM), such as an electrically erasable programmable read-only memory (EEPROM). Conventional techniques for including non-volatile memory on the same Complementary Metal Oxide Semiconductor (CMOS) integrated circuit as the data processing unit have utilized the gate oxide of CMOS process to instantiate a logic-based single polysilicon floating gate EEPROM. The inventors of the embodiments of the present disclosure have recognized that such embedded single polysilicon EEPROM cells typically require separate control gate and floating gate transistors, as well as their isolation, from the access transistors and the state transistors. In connection therewith, the inventors of embodiments of the present disclosure have also recognized that the footprint of such embedded single polysilicon EEPROM cells is typically large, thus consuming a substantial area of the semiconductor die. Other NVM technologies using multiple polysilicon layers have been designed to have smaller footprints than single polysilicon EEPROM cells. The inventors of embodiments of the present disclosure have recognized that such other NVM technologies have higher processing costs and lower reliability. Embodiments of the present disclosure may address one or more of these challenges. Disclosure of Invention According to one aspect of the present disclosure, a non-volatile memory NVM bitcell is provided, the NVM bitcell including a control gate including a floating terminal formed from a first polysilicon layer, a control terminal formed from a second polysilicon layer, and a control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer includes a high-K dielectric layer, a state transistor including a floating gate terminal formed from the first polysilicon layer and coupled to the floating terminal of the control gate, and a tunnel oxide layer formed between the first polysilicon layer and an active region of the state transistor, and an access transistor coupled in series with the state transistor. According to another aspect of the present disclosure, an integrated circuit is provided that includes a logic block, and a non-volatile memory NVM bitcell array coupled to the logic block, the NVM bitcell array including a plurality of NVM bitcells arranged in a plurality of rows and columns, each NVM bitcell including a control gate including a floating terminal formed from a first polysilicon layer, a control terminal formed from a second polysilicon layer, and a control gate dielectric layer formed between the first polysilicon layer and the second polysilicon layer, wherein the control gate dielectric layer includes a high-K dielectric layer, a state transistor including a floating gate terminal formed from the first polysilicon layer and coupled to the floating terminal of the control gate, and a tunnel oxide layer formed between the first polysilicon layer and the active region of the state transistor, and the access transistor coupled in series with the state transistor. According to yet another aspect of the present disclosure, a method is provided that includes forming a well region, forming an access transistor in the well region, forming a state transistor in the well region, the state transistor having a floating gate terminal formed from a first polysilicon layer, forming a control gate having a floating terminal formed from the first polysilicon layer, a control terminal formed from a second polysilicon layer, and a control gate dielectric layer disposed between the first polysilicon layer and the second polysilicon layer and including a high-K dielectric layer. Drawings A more complete understanding of the present embodiments may be obtained by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features. Fig. 1 shows a block diagram of an integrated circuit according to an embodiment of the present disclosure. Fig. 2 shows a schematic diagram of a non-volatile memory bitcell according to an embodiment of the present disclosure. Fig. 3 is a graph illustrating operating conditions of a non-volatile memory bitcell according to an embodiment of the present disclosure. Fig. 4 illustrates a top view of a semiconductor process region for a non-volatile memory bitcell array in accordance with an embodiment of the present disclosure. Fig. 5