CN-122024793-A - Memory programming control circuit

Abstract

The memory programming control circuit comprises a main counter, N registers, N D-type flip-flops, an updating control unit, a group counter and a writing control unit. The master counter increments the master counter value according to the clock signal. The N registers store N bits to be written to the memory. The update control unit sequentially updates the N D-type flip-flops with the data stored in the N registers as the master counter value increases, and the write buffer is updated with the bits stored in the corresponding D-type flip-flops when the DFF is updated. Each time the D-type flip-flop is updated with the first type bit, the group counter is incremented by the group counter value, and when the group counter value reaches M, a group write enable signal is generated, thereby causing the write control unit to perform a group write operation on the memory.

Inventors

• ZHANG JIAFU
• PENG RENYOU

Assignees

• 力旺电子股份有限公司

Dates

Publication Date

20260512

Application Date

20251111

Priority Date

20241112

Claims (20)

1. 1. A memory programming control circuit, comprising: A master counter configured to increment a master counter value according to a clock signal; N registers configured to store N bits of a word to be written to the memory, where N is an integer greater than 1; N D-type flip-flops coupled to N write buffers of the memory; An update control unit coupled to the N registers and configured to update the N D-type flip-flops one by one with the N bits stored in the N registers as the master counter value increases, wherein a write buffer of the N write buffers is updated with bits stored in the corresponding D-type flip-flops as a corresponding D-type flip-flop of the N D-type flip-flops is updated; A group counter coupled to the refresh control unit and configured to increment a group counter value each time a D-flip-flop of the N D-flip-flops is updated with a first type bit, and generate a first group write enable signal to request the write control unit of the memory to perform a first group write operation to write a plurality of bits stored in a plurality of write buffers of the N write buffers to the memory when the group counter value reaches M, wherein M is less than N, and A master control unit configured to generate the clock signal to the master counter.
2. 2. The memory programming control circuit of claim 1, wherein the master control unit is further configured to reset the group counter value after the first group write enable signal has been generated.
3. 3. The memory programming control circuit of claim 1, wherein the master control unit is further configured to generate a second group write enable signal to the write control unit when the master counter value reaches N, thereby causing the write control unit to perform a second group write operation to write at least one data stored in at least one of the N write buffers to the memory.
4. 4. The memory programming control circuit of claim 3, wherein the master control unit is further configured to reset the master counter value and the group counter value after the second group write enable signal has been generated.
5. 5. The memory programming control circuit of claim 1, wherein the write control unit or the master control unit is further configured to reset the plurality of write buffers of the N write buffers after the first group write operation has been completed.
6. 6. The memory programming control circuit of claim 1, wherein the master control unit stops switching of the clock signal during the first group write operation to stop the master counter from incrementing and resumes switching of the clock signal after the first group write operation is completed to continue the master counter to increment.
7. 7. The memory programming control circuit of claim 1, wherein M corresponds to a maximum number of memory cells that the memory allows to be programmed simultaneously.
8. 8. The memory programming control circuit of claim 1, wherein the memory is a non-volatile memory.
9. 9. The memory programming control circuit of claim 1, wherein the refresh control unit comprises: n switches, each having an input coupled to one of the N registers and an output coupled to a common node, wherein the data inputs of the N D-flip-flops are coupled to the common node, and And a decoder configured to generate N control signals to control the N switches according to the master counter value, thereby allowing the N D-type flip-flops to be updated one by N bits stored in the N registers as the master counter value increases.
10. 10. The memory programming control circuit of claim 9, wherein each of the N D-type flip-flops has a clock terminal configured to receive a control signal of the N control signals.
11. 11. The memory programming control circuit of claim 1, wherein the memory cells of the memory store a second type of bits different from the first type prior to programming the memory cells.
12. 12. A method of writing data to a memory, comprising: Storing N bits of a word to be written into the memory in N registers, wherein N is an integer greater than 1; Increasing a master counter value according to the clock signal; updating N D-type flip-flops with the N bits stored in the N registers one by one as the master counter value increases; Updating a write buffer of the N write buffers by bits stored in a corresponding D-flip flop as the corresponding D-flip flop of the N D-flip flops is updated; each time a D-flip-flop of the N D-flip-flops is updated with a first type bit, increasing a group counter value, and When the group counter value reaches M, a first group write enable signal is generated, and a first group write operation is performed on the memory to write a plurality of bits stored in a plurality of write buffers of the N write buffers into the memory, wherein M is less than N.
13. 13. The method of claim 12, further comprising: after generating the first group write enable signal, the group counter value is reset.
14. 14. The method of claim 12, further comprising: When the master counter reaches N, a second group write enable signal is generated, and a second group write operation is performed on the memory to write at least one data stored in at least one of the N write buffers into the memory.
15. 15. The method of claim 14, further comprising: After generating the second group write enable signal, the master counter value and the group counter value are reset.
16. 16. The method of claim 12, further comprising: After the first group write operation is completed, the plurality of write buffers of the N write buffers are reset.
17. 17. The method of claim 12, wherein the clock signal stops switching during the first group write operation.
18. 18. The method of claim 12, wherein M corresponds to a maximum number of memory cells that the memory allows to be programmed simultaneously.
19. 19. The method of claim 12, wherein the memory is a non-volatile memory.
20. 20. The method of claim 12, wherein the memory cells of the memory store a second type of bits different from the first type prior to programming the memory cells.

Description

Memory programming control circuit Technical Field The present disclosure relates to a memory programming control circuit, and more particularly, to a memory programming control circuit capable of reducing memory writing time. Background A Non-volatile memory (NVM) is a memory that retains stored information even when power is turned off. Such characteristics make nonvolatile memory critical for applications requiring data persistence. Common examples of non-volatile memory include flash memory, electrically Erasable Programmable Read Only Memory (EEPROM), and magnetoresistive random access memory (Magnetoresistive random access memory, MRAM). These memories can be used to reliably store firmware, user data, and system configuration without requiring constant power. However, during a programming operation of a non-volatile memory, a high voltage is typically required to change the storage state of the memory cell. For example, programming operations may involve injecting electrons into the floating gate or damaging the gate structure with high voltages, which may also produce significant current. Based on the requirements for high voltage and high current, systems typically have limitations on the number of bits that can be programmed simultaneously. In this case, bit programming can only be performed in smaller groups, and such limitations result in longer programming times. Therefore, how to reduce the programming time of the nonvolatile memory has become a critical issue to be resolved in the field. The background information is provided only in the "prior art" paragraph. The statement of this "prior art" does not constitute an admission that the subject matter disclosed in this paragraph constitutes prior art with respect to the present disclosure, and any part of this "prior art" paragraph is considered an admission that any part of the present disclosure (including this "prior art" paragraph) constitutes prior art with respect to the present disclosure. Disclosure of Invention One aspect of the present disclosure provides a memory programming control circuit. The memory programming control circuit includes a master counter, N registers, N D flip-flops (D flip-flops, DFFs), an update control unit, a group counter, and a master control unit. The master counter increments the master counter value according to the clock signal. The N registers store N bits of a word to be written into the memory, where N is an integer greater than 1. The N D-type flip-flops are coupled to N write buffers of the memory. The update control unit is coupled to the N registers. As the master counter value increases, the update control unit updates N D-type flip-flops one by one with N bits stored in N registers. With a corresponding D-flip-flop being updated, a write buffer of the N write buffers is updated by bits stored in the corresponding D-flip-flop of the N D-flip-flops. The group counter is coupled to the update control unit. Each time a D-flip-flop of the N D-flip-flops is updated with a first type bit, the group counter increases the group counter value, and when the group counter value reaches M, a first group write enable signal is generated to request a write control unit of the memory to perform a first group write operation to write a plurality of bits stored in a plurality of write buffers of the N write buffers into the memory, wherein M is smaller than N. The main control unit generates a clock signal to the main counter. Another aspect of the present disclosure provides a method of writing data to a memory. The method includes storing N bits of a word to be written into a memory in N registers, increasing a master counter value according to a clock signal, updating N D-type flip-flops one by one with N bits stored in the N registers as the master counter value increases, updating a write buffer of N write buffers with bits stored in a corresponding D-type flip-flop as a corresponding D-type flip-flop is updated, increasing a group counter value each time a D-type flip-flop of N is updated with a first type bit, and generating a first group write enable signal when the group counter value reaches M, performing a first group write operation on the memory to write the N bits stored in the N write buffers into the memory, wherein N is an integer greater than 1 and M is less than N. Drawings The present disclosure will become more fully understood from the detailed description and the claims, wherein like reference numerals refer to like elements throughout, and the accompanying drawings. FIG. 1 shows a non-volatile memory cell according to an embodiment of the disclosure; FIG. 2 shows bias voltages provided to the memory cell of FIG. 1 when performing a programming operation; FIG. 3 shows the bias voltage provided to the memory cell of FIG. 1 when a read operation is performed; FIG. 4 shows a memory according to an embodiment of the present disclosure; FIG. 5 shows a memory programming control circuit according t