CN-122024794-A - Memory array of SONOS memory and programming method thereof

Abstract

The invention provides a memory array of a SONOS memory and a programming method thereof, wherein a memory unit of the memory array comprises a selection tube and four memory tubes uniformly distributed on two sides of the selection tube, and the four memory tubes are distributed on two sides of the selection tube in a split-gate structure, so that the memory area can be greatly reduced, and the memory density can be improved. Furthermore, the programming method of the SONOS memory array provided by the invention supports two rows on two sides of the selection tube word line in the same memory cell to write simultaneously, improves the writing efficiency, and because the selection tube word line is turned off during writing, the voltages transmitted by the source line or the bit line respectively regulate and control the writing contents of the memory gates on two sides of the selection tube word line, the two writing contents are not mutually influenced during writing, and the source line or the bit line can be set according to the writing contents without floating.

Inventors

• WANG NING
• ZHANG KEGANG

Assignees

• 上海华虹宏力半导体制造有限公司

Dates

Publication Date

20260512

Application Date

20260127

Claims (20)

1. 1. A memory array of a SONOS memory device, comprising: the memory cells are arranged in an array manner, and share one memory tube well of the substrate; The memory unit comprises a selection tube and four memory tubes which are evenly distributed on two sides of the selection tube, wherein the selection tube and the memory tubes are connected in series, two memory tubes adjacent to the selection tube share a source electrode or a drain electrode, and the source electrode or the drain electrode of the two memory tubes far away from the selection tube is connected to a corresponding source line or bit line; In the X direction, the storage gates of the storage tubes in the same row are connected out through a storage tube word line, and the selection gates of the selection tubes in the same row are connected out through a selection tube word line; in the Y-direction, the memory cells of the same column share a set of source and bit lines.
2. 2. The memory array of claim 1, wherein an isolation layer is disposed between the memory gates of two memory tubes on one side of the select gate of the select tube, an isolation oxide layer and a memory medium layer are disposed between the select gate and the adjacent memory gate, and an isolation oxide layer and a sidewall are disposed on the outer sides of the two memory gates far from the select gate.
3. 3. The memory array of claim 2, wherein a memory tube threshold voltage adjustment region is disposed below a surface of the memory tube well, the memory tube threshold voltage adjustment region being disposed below the select gate and a storage medium layer being disposed between the memory tube threshold voltage adjustment region and the select gate.
4. 4. The memory array of claim 3, wherein a source-drain lightly doped region and a source-drain region are disposed below the surface of the memory tube well, the source-drain lightly doped region is disposed below the isolation layer and the sidewall, and the source-drain region is disposed between two memory cells, corresponding to a source line or a bit line.
5. 5. The memory array of claim 4, wherein the memory cell further comprises a gate oxide layer, the gate oxide layer being located between the select gate, the isolation oxide layer, and the sidewall and the substrate.
6. 6. The memory array of claim 4, wherein the memory gates on one side of the select gates are symmetrically distributed about the spacer layer in the memory cell.
7. 7. The memory array of claim 4, wherein the memory cells are N-type, the memory pipe well is a P-well, and the source-drain lightly doped regions and the source-drain regions are N-type doped regions.
8. 8. The method of programming a memory array of a SONOS memory device of any one of claims 1 to 7, wherein the memory array is erased or written in rows, and wherein the data of each of the memory cells is read individually.
9. 9. The method of programming a memory array of a SONOS memory device of claim 8, wherein the method of programming comprises, when performing an erase operation: a storage tube trap voltage VposE; all source and bit lines are connected to voltage VposE; the memory gate of the selected row is connected with voltage VnegE; the storage gate voltages VposE of all non-selected rows; all select gates are connected to voltage VposE.
10. 10. The method of claim 8, wherein the voltage VposE is in the range of 3V to 5V and the voltage VnegE is in the range of-5V to-3V.
11. 11. The method of programming a memory array of SONOS memory device of claim 8, wherein the method of programming comprises, upon a write operation to a row proximate to a source line or a bit line: A storage tube trap voltage VnegP; All select gate voltages VnegP; the memory gate of the selected row is connected with voltage VposP; The storage gate voltages VnegU of all non-selected rows; The source or bit line near the selected row controls the write content, when writing 1, the source or bit line is tied to voltage VnegP, when writing 0, the source or bit line is tied to voltage VPI, and the source or bit line not near the selected row is floating.
12. 12. The method of programming a memory array of SONOS memory device of claim 8, wherein the method of programming comprises, upon a write operation to a row proximate to a select pipe word line: A storage tube trap voltage VnegP; All select gate voltages VnegP; the memory gate of the selected row is connected with voltage VposP; a memory gate voltage VpassP adjacent to the selected row in the selected memory cell; All other unselected rows store gate voltages VnegU; The source or bit line near the selected row controls the write content, when writing 1, the source or bit line is tied to voltage VnegP, when writing 0, the source or bit line is tied to voltage VPI, and the source or bit line not near the selected row is floating.
13. 13. The method of programming a memory array of a SONOS memory device of claim 8, wherein the method of programming comprises, when writing any two rows on either side of a select pipe word line simultaneously: A storage tube trap voltage VnegP; All select gate voltages VnegP; the memory gate of the selected row is connected with voltage VposP; In the selected memory cell, a memory gate voltage VpassP adjacent to the selected row near the source line or bit line; All other unselected rows store gate voltages VnegU; the memory pipe word line is turned off, the source line or bit line controls the writing content, and when 1 is written, the source line or bit line is connected with voltage VnegP, and when 0 is written, the source line or bit line is connected with voltage VPI.
14. 14. The method of programming a memory array structure of a SONOS memory device according to any one of claims 11 to 13, wherein the voltage VnegP V to 3V, the voltage VposP ranges from 4V to 6V, the voltage VnegU ranges from-4V to-2V, the voltage VPI ranges from 0.5V to 2V, and the voltage VpassP ranges from-2V to 0V.
15. 15. The method of claim 14, wherein the voltage VnegP V, the voltage VposP V, the voltage VnegU V, the voltage VPI 1.2V and the voltage VpassP V are-3.6V, 4.5V, 2.6V, and 1.1V respectively.
16. 16. The method of programming a memory array of a SONOS memory device of claim 8, wherein the method of programming comprises, in performing a read operation: a storage tube trap voltage Vgnd; the selection gate and the storage gate of the unselected storage unit are both connected with voltage Vnd; The selection gate voltage Vpos1R of the selected memory cell; The storage gate ground voltage Vgnd of the selected row; the non-selected row in the selected memory cells stores the gate voltage Vpos2R; In the selected memory cell, the source line or bit line adjacent to the selected row is connected to the voltage Vgnd, and the source line or bit line adjacent to the selected row is connected to the voltage Vpos3R, and the source line or bit line adjacent to the other non-selected columns is connected to the voltage Vgnd.
17. 17. The method of programming a memory array of a SONOS memory device of claim 16, wherein the voltage Vpos1R ranges from 1.5V to 3V, the voltage Vpos2R ranges from 2V to 3V, the voltage Vpos3R ranges from 0.4V to 1.2V, and the voltage Vgnd is 0V.
18. 18. The method of programming a memory array of a SONOS memory device of claim 17, wherein the voltage Vpos1R is 2.5V, the voltage Vpos2R is in a range of 2.5V, and the voltage Vpos3R is in a range of 0.6V.
19. 19. The method of programming a memory array of SONOS memory device of claim 16, wherein the voltage Vpos1R is greater than a threshold voltage of a select transistor.
20. 20. The method of programming a memory array of SONOS memory device of claim 16, wherein the voltage Vpos2R is greater than a threshold voltage of the memory cell in a write 1 state.

Description

Memory array of SONOS memory and programming method thereof Technical Field The present invention relates to the field of semiconductor integrated circuit manufacturing technology, and in particular, to a memory array of a SONOS memory and a programming method thereof. Background With the development of technology, the requirement for storing and processing data is higher and higher for analysis of large data, and thus, the nonvolatile memory is also increased. Nonvolatile memory is an indispensable storage device in a computer and plays an important role in storing processed information. Among nonvolatile memories, SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memories have advantages of small cell size, good memory retention, low operating voltage, compatibility with Complementary Metal Oxide Semiconductor (CMOS) manufacturing processes, and the like, and are widely used in electronic products. In the existing 2T SONOS memory, a memory cell is composed of a SONOS memory tube and a selection tube, and in the 2T SONOS memory, the low power consumption is favored by many applications. However, the inherent disadvantage of the conventional 2T SONOS memory cell is its larger chip area loss, while the smaller the memory cell area, the lower the cost, and the more competitive it is in the same product. In view of the above, the present invention provides a memory array of a SONOS memory and a programming method thereof. Disclosure of Invention The invention aims to provide a storage array structure of a SONOS memory to solve the problems of larger storage unit area and low storage density of the existing SONOS memory. Another objective of the present invention is to provide a method for programming a memory array of a SONOS memory, where the method supports simultaneous writing of two rows located on both sides of a select transistor word line in the same memory cell, thereby improving the writing efficiency. To achieve the above object, the present invention provides a memory array of a SONOS memory, comprising: the memory cells are arranged in an array manner, and share one memory tube well of the substrate; The memory unit comprises a selection tube and four memory tubes which are evenly distributed on two sides of the selection tube, wherein the selection tube and the memory tubes are connected in series, two memory tubes adjacent to the selection tube share a source electrode or a drain electrode, and the source electrode or the drain electrode of the two memory tubes far away from the selection tube is connected to a corresponding source line or bit line; In the X direction, the storage gates of the storage tubes in the same row are connected out through a storage tube word line, and the selection gates of the selection tubes in the same row are connected out through a selection tube word line; in the Y-direction, the memory cells of the same column share a set of source and bit lines. In some optional embodiments, in the memory unit, an isolation layer is disposed between the memory gates of the two memory tubes located at one side of the selection gate of the selection tube, an isolation oxide layer and a memory medium layer are disposed between the selection gate and the adjacent memory gate, and an isolation oxide layer and a sidewall are disposed at outer sides of the two memory gates far from the selection gate. In some alternative embodiments, a storage tube threshold voltage adjustment region is disposed below the surface of the storage tube well in the storage unit, and a storage medium layer is disposed between the storage tube threshold voltage adjustment region and the selection gate. In some optional embodiments, a source-drain lightly doped region and a source-drain region are arranged below the surface of the storage tube well, the source-drain lightly doped region is arranged below the isolation layer and the side wall, and the source-drain region is arranged between two storage units and corresponds to a source line or a bit line. In some alternative embodiments, the memory cell further includes a gate oxide layer, where the gate oxide layer is located between the select gate, the isolation oxide layer, and the sidewall and the substrate. In some alternative embodiments, in the memory cell, the memory gates located at one side of the selection gate are symmetrically distributed with respect to the isolation layer. In some optional embodiments, the memory cell is N-type, the memory tube well is a P-well, and the source-drain lightly doped region and the source-drain region are N-type doped regions. Based on the same inventive concept, the invention also provides a programming method of the memory array of the SONOS memory, wherein the memory array is erased or written in according to rows, and the data of each memory tube are read independently during reading. In some alternative embodiments, the programming method of the memory array of the SONOS memory device includes, when performing an er