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CN-122024795-A - Data storage device and decoding combination selection method

CN122024795ACN 122024795 ACN122024795 ACN 122024795ACN-122024795-A

Abstract

A data storage device comprises a nonvolatile memory and a processing circuit, wherein the nonvolatile memory comprises a plurality of blocks, each block comprises a plurality of pages, the decoding combination selection method is executed by the processing circuit and comprises the steps of periodically reading any page in the nonvolatile memory to update a state parameter of a first block comprising the any page in a block state table, and selecting one of a plurality of decoding combinations according to the state parameter of the first block in the block state table to decode the first block, wherein the state parameter comprises a charge leakage degree value, a potential offset degree value, a first offset voltage and a second offset voltage, and a first bit number and a second bit number corresponding to the first offset voltage and the second offset voltage respectively.

Inventors

  • LI FAHAO

Assignees

  • 慧荣科技股份有限公司

Dates

Publication Date
20260512
Application Date
20241111

Claims (10)

  1. 1. A decoding combination selection method of a data storage device, wherein the data storage device includes a nonvolatile memory and a processing circuit, the nonvolatile memory includes a plurality of blocks, each block includes a plurality of pages, the decoding combination selection method is executed by the processing circuit to include: Periodically reading any page in the non-volatile memory to update the state parameters of a first block in a block state table including the any page, and Selecting one of a plurality of decoding combinations according to the state parameters of the first block in the block state table to decode the first block; The state parameter includes a charge leakage degree value, a potential offset degree value, a first offset voltage and a second offset voltage, and a first bit number and a second bit number corresponding to the first offset voltage and the second offset voltage, respectively.
  2. 2. The method for decoding combination selection of a data storage device according to claim 1, and periodically reading any page in the non-volatile memory through the first offset voltage and the second offset voltage to obtain the first bit number and the second bit number of one bit.
  3. 3. The decoding combination selection method of a data storage device according to claim 2, wherein the first number of bits and the second number of bits are numbers of bits 0 or 1.
  4. 4. The method of claim 1, wherein a third offset voltage and hard decoding are selected to decode the first block based on the magnitude of the charge leakage for the first block in the block state table being less than or equal to a first threshold, and the third offset voltage and soft decoding are selected to decode the first block based on the magnitude of the charge leakage for the first block in the block state table being greater than the first threshold.
  5. 5. The method of claim 1, wherein a fourth offset voltage and hard decoding are selected to decode the first block according to the magnitude of the potential offset of the first block in the block state table being less than or equal to a second threshold, and a fifth offset voltage and soft decoding are selected to decode the first block according to the magnitude of the potential offset of the first block in the block state table being greater than the second threshold.
  6. 6. A data storage device, comprising: a non-volatile memory, and The processing circuit is coupled with the nonvolatile memory; wherein the processing circuit performs a decoding combination selection method of a data storage device comprising: Periodically reading any page in the non-volatile memory to update the state parameters of a first block in a block state table including the any page, and Selecting one of a plurality of decoding combinations according to the state parameters of the first block in the block state table to decode the first block; The state parameter includes a charge leakage degree value, a potential offset degree value, a first offset voltage and a second offset voltage, and a first bit number and a second bit number corresponding to the first offset voltage and the second offset voltage, respectively.
  7. 7. The data storage device of claim 6, wherein the first number of bits and the second number of bits of one bit are obtained by periodically reading the arbitrary page in the non-volatile memory with the first offset voltage and the second offset voltage.
  8. 8. The data storage device of claim 7, wherein the first number of bits and the second number of bits are numbers of bits 0 or 1.
  9. 9. The data storage device of claim 6, wherein a third offset voltage and hard decoding are selected to decode the first block based on the charge leakage level value of the first block in the block state table being less than or equal to a first threshold, and wherein the third offset voltage and soft decoding are selected to decode the first block based on the charge leakage level value of the first block in the block state table being greater than the first threshold.
  10. 10. The data storage device of claim 6, wherein a fourth offset voltage and hard decoding are selected to decode the first block based on the magnitude of the potential offset for the first block in the block state table being less than or equal to a second threshold, and a fifth offset voltage and soft decoding are selected to decode the first block based on the magnitude of the potential offset for the first block in the block state table being greater than the second threshold.

Description

Data storage device and decoding combination selection method Technical Field The present invention relates to a data storage device and a data decoding method, and more particularly, to a data storage device and a decoding combination selection method. Background Flash memory is a non-volatile memory and has the characteristic of no data loss after power failure. Unlike conventional Random Access Memory (RAM), flash memory cannot be re-written, cannot be modified directly from the original data, but requires that the entire block be erased before new data is written. The basic memory cells in flash memory are "cells", a plurality of cells form "pages", a plurality of pages form blocks, a plurality of blocks form "planes", a plurality of planes form "cores", and finally a flash memory chip (NAND FLASH) is formed. The page is the minimum unit of the flash memory for reading and writing. The "block" in the flash memory refers to a basic unit of the flash memory chip for an erase operation. Since the erase operation is performed in units of blocks, not byte by byte, additional operations may be generated when updating data, affecting the write performance. However, this approach may enable the flash memory chip to manage the storage space more efficiently when storing large amounts of data. In flash memory, a "first read problem" generally refers to an abnormality that a piece of data is read for the first time after being written into the flash memory, such as inaccuracy, instability, or slower reading speed than a subsequent reading operation. Possible causes of the first read problem are unstable charge distribution, imperfect initialization, insufficient precharge, etc. How to solve the first reading problem of the flash memory and at the same time know the status of each block in the flash memory to provide a decoding combination adapted to the status of the flash memory is a technical problem to be solved in the art. Disclosure of Invention The invention provides a data storage device and a decoding combination selection method thereof, which can solve the first reading problem of a flash memory and simultaneously know the condition of each block in the flash memory so as to provide decoding combination suitable for the state of the flash memory. The data storage device comprises a non-volatile memory and a processing circuit coupled with the non-volatile memory, wherein the processing circuit executes a decoding combination selection method of the data storage device, and the method comprises the steps of periodically reading any page in the non-volatile memory to update a state parameter of a first block comprising the any page in a block state table, and selecting one of a plurality of decoding combinations according to the state parameter of the first block in the block state table to decode the first block, wherein the state parameter comprises a charge leakage degree value, a potential offset degree value, a first offset voltage, a second offset voltage, a first bit number and a second bit number which respectively correspond to the first offset voltage and the second offset voltage. The invention provides a decoding combination selection method of a data storage device, wherein the data storage device comprises a nonvolatile memory and a processing circuit, the nonvolatile memory comprises a plurality of blocks, each block comprises a plurality of pages, the decoding combination selection method is executed by the processing circuit and comprises the steps of periodically reading any page in the nonvolatile memory to update a state parameter of a first block comprising any page in a block state table, and selecting one of a plurality of decoding combinations according to the state parameter of the first block in the block state table to decode the first block, wherein the state parameter comprises a charge leakage degree value, a potential offset degree value, a first offset voltage and a second offset voltage, and a first bit number and a second bit number which respectively correspond to the first offset voltage and the second offset voltage. In an embodiment of the present invention, the first offset voltage and the second offset voltage are used to periodically read the arbitrary page in the non-volatile memory to obtain a first bit number and a second bit number of one bit. In an embodiment of the present invention, the first number of bits and the second number of bits are numbers of bits 0 or 1. In one embodiment of the invention, the third offset voltage and the hard decoding are selected to decode the first block according to the charge leakage level value of the first block in the block state table being less than or equal to the first threshold value, and the third offset voltage and the soft decoding are selected to decode the first block according to the charge leakage level value of the first block in the block state table being greater than the first threshold value. In one embodime