CN-122024797-A - Nonvolatile flash memory and data concurrent or processing method

Abstract

The invention provides a nonvolatile flash memory and a data concurrent or processing method, comprising a first latch, a second latch and a third latch, wherein the first latch is used for storing written first data and concurrent or operated result data; the bit line buffer is used for storing intermediate data generated in the AND operation by utilizing bit lines in the nonvolatile flash memory. The bit line is used as an additional latch to store the generated intermediate data, and the bit line capacitance is of the picofarad magnitude, so that the data stored on the bit line can be kept for a long time relative to microsecond operation without additional electric leakage, and the intermediate data storage requirement in the hold write data hold or operation is met.

Inventors

• ZHOU LIN

Assignees

• 至讯创新科技(无锡)有限公司

Dates

Publication Date

20260512

Application Date

20260203

Claims (15)

1. 1. A non-volatile flash memory, comprising: the first latch is used for storing first data written into the flash memory array by a user and result data after exclusive OR operation; a second latch for storing second data desired by a user; and the bit line buffer is used for storing intermediate data generated in the AND operation by utilizing bit lines in the nonvolatile flash memory.
2. 2. The non-volatile flash memory of claim 1, wherein adjacent ones of the bit lines in the non-volatile flash memory are isolated from each other, and wherein the bit lines in the odd bits do not participate in the operation or the bit lines in the even bits do not participate in the operation.
3. 3. The non-volatile flash memory of claim 1, wherein the bit line buffer comprises a first bit line transistor, a second bit line transistor, a third bit line transistor, a fourth bit line transistor, a fifth bit line transistor, a sixth bit line transistor, and a seventh bit line transistor; The source electrode of the first bit line transistor is connected with a power supply, the drain electrode of the first bit line transistor is connected with the source electrode of the second bit line transistor and the source electrode of the third bit line transistor, the drain electrode of the second bit line transistor is connected with the drain electrode of the fourth bit line transistor, the drain electrode of the third bit line transistor is connected with the source electrode of the fifth bit line transistor, the source electrode of the fourth bit line transistor is connected with the source electrode of the sixth bit line transistor and the drain electrode of the seventh bit line transistor, the drain electrode of the fifth bit line transistor is connected with the drain electrode of the sixth bit line transistor, the source electrode of the seventh bit line transistor is connected with page cache data, the gate electrode of the third bit line transistor and the drain electrode of the sixth bit line transistor are connected with the first latch, and the source electrode of the sixth bit line transistor is connected with the second latch.
4. 4. The non-volatile flash memory of claim 3, wherein the memory cells are configured to store data corresponding to the data, the first bit line transistor, the second bit line transistor the third bit line transistor and the fifth bit line transistor are PMOS; the fourth bit line transistor, the sixth bit line transistor, and the seventh bit line transistor are NMOS.
5. 5. The non-volatile flash memory of claim 3, further comprising a verification controller, wherein the verification controller is configured to control a storage state of the bit line buffer.
6. 6. The non-volatile flash memory of claim 5, wherein the verification controller comprises a first verification transistor, a second verification transistor, and a third verification transistor; The drain electrode of the first verification transistor is connected with the source electrode of the sixth bit line transistor, the source electrode of the first verification transistor is connected with the drain electrode of the second verification transistor and the source electrode of the third verification transistor, the grid electrode of the second verification transistor is connected with the first latch, the source electrode of the second verification transistor is connected with a power supply, and the drain electrode of the third verification transistor is connected with expected data.
7. 7. The non-volatile flash memory of claim 6, wherein the first, second, and third verify transistors are NMOS.
8. 8. A data synchronization or processing method applied to the nonvolatile flash memory according to any one of claims 1 to 7, wherein the data synchronization or processing method comprises: reading first data from the first latch and storing the first data in the bit line buffer; Adjusting the state of the bit line buffer according to the first data; Reading second data from the second latch; Adjusting the state of the bit line buffer according to the second data; The first data in the first latch is modified according to the state adjustment result of the bit line buffer to obtain result data.
9. 9. The data-exclusive-nor processing method according to claim 8, wherein the data-exclusive-nor processing method further comprises: reading first data from the bit line buffer, and adjusting the state of the bit line buffer according to the first data; Adjusting the state of the bit line buffer according to the second data; and modifying the first data in the first latch again according to the state adjustment result of the bit line buffer to obtain result data.
10. 10. The data exclusive or processing method according to claim 8, wherein the method of reading the first data from the first latch and storing the first data in the bit line buffer includes: if the first data is 1, the corresponding stored intermediate data in the bit line buffer is 0; if the first data is 0, the intermediate data stored in the bit line buffer is 1.
11. 11. The data exclusive-nor processing method according to claim 8, wherein the method of adjusting the state of the bit line buffer according to the first data includes: If the intermediate data stored in the bit line buffer is 1, the internal node of the bit line buffer is 1; if the intermediate data stored in the bit line buffer is 0, the internal node of the bit line buffer is 0; The state of the bit line buffer is adjusted to charge the internal node of the bit line buffer to 1 and keep the intermediate data stored on the bit line buffer unchanged.
12. 12. The data exclusive-nor processing method according to claim 8 or 9, wherein the method of adjusting the state of the bit line buffer according to the second data includes: If the second data is 1, discharging the internal node of the bit line buffer to 0, and keeping the intermediate data stored in the bit line buffer unchanged; If the second data is 0, the internal node of the bit line buffer and the stored intermediate data are kept unchanged.
13. 13. The data exclusive-nor processing method according to claim 8, wherein the method of modifying the first data in the first latch according to the state adjustment result of the bit line buffer to obtain the result data includes: Modifying the first data in the first latch to 0 if the internal node of the bit line buffer is 1; if the internal node of the bit line buffer is 0, the first data in the first latch is kept unchanged.
14. 14. The data exclusive-nor processing method according to claim 9, wherein the method of reading the first data from the bit line buffer and adjusting the state of the bit line buffer according to the first data includes: If the first data is read as 1 from the bit line buffer, the internal node of the bit line buffer is 1; if the first data is read from the bit line buffer as 0, the internal node of the bit line buffer is 0.
15. 15. The data exclusive-nor processing method according to claim 9, wherein the method of modifying the first data in the first latch again according to the state adjustment result of the bit line buffer to obtain the result data includes: if the internal node of the bit line buffer is 1, modifying the first data in the first latch to be 1; if the internal node of the bit line buffer is 0, the first data in the first latch is kept unchanged.

Description

Nonvolatile flash memory and data concurrent or processing method Technical Field The present invention relates to the field of data processing technologies, and in particular, to a nonvolatile flash memory and a data synchronization or processing method. Background Page buffers (page buffers) in nonvolatile flash memory (NAND flash) are used to temporarily store data written by a user or data read from a flash memory array. As the page buffer capacity increases, the proportion of write operations or read operations occupying the entire NAND flash operation increases. In order to reduce the time taken by the write operation and the read operation, the NAND flash memory performs an exclusive nor operation (XNOR) internally, that is, compares the written data with the read data, and if the two data are identical, the feedback is successful, otherwise, the feedback fails. When the XNOR operation is performed in the NAND flash memory, the same page data can be copied to the whole flash memory block (block) or the whole flash memory chip, and if the data written by a user can be reserved when the XNOR operation is performed, the user only needs to write the expected data once, and the data comparison of the whole flash memory block in the NAND flash memory and even the whole flash memory chip can be completed. However, if the exclusive nor operation is to be performed, at least three latches are required in the NAND flash memory, wherein one latch is used to store the data written by the user, one latch is used to store the read data, and at least one latch is used to store the intermediate data. This clearly increases the area and manufacturing cost of the NAND flash memory chip. Disclosure of Invention The invention aims to provide a nonvolatile flash memory and a data exclusive nor processing method, which are used for solving the problem of how to realize exclusive nor operation of the nonvolatile flash memory for reserving writing data on the basis of not increasing the chip area and the cost. In order to solve the above technical problems, the present invention provides a nonvolatile flash memory, comprising: the first latch is used for storing first data written into the flash memory array by a user and result data after exclusive OR operation; a second latch for storing second data desired by a user; and the bit line buffer is used for storing intermediate data generated in the AND operation by utilizing bit lines in the nonvolatile flash memory. Optionally, in the nonvolatile flash memory, adjacent bit lines are isolated from each other, and bit lines in odd bits do not participate in operation, or bit lines in even bits do not participate in operation. Optionally, in the nonvolatile flash memory, the bit line buffer includes a first bit line transistor, a second bit line transistor, a third bit line transistor, a fourth bit line transistor, a fifth bit line transistor, a sixth bit line transistor, and a seventh bit line transistor; The source electrode of the first bit line transistor is connected with a power supply, the drain electrode of the first bit line transistor is connected with the source electrode of the second bit line transistor and the source electrode of the third bit line transistor, the drain electrode of the second bit line transistor is connected with the drain electrode of the fourth bit line transistor, the drain electrode of the third bit line transistor is connected with the source electrode of the fifth bit line transistor, the source electrode of the fourth bit line transistor is connected with the source electrode of the sixth bit line transistor and the drain electrode of the seventh bit line transistor, the drain electrode of the fifth bit line transistor is connected with the drain electrode of the sixth bit line transistor, the source electrode of the seventh bit line transistor is connected with page cache data, the gate electrode of the third bit line transistor and the drain electrode of the sixth bit line transistor are connected with the first latch, and the source electrode of the sixth bit line transistor is connected with the second latch. Optionally, in the nonvolatile flash memory, the first bit line transistor, the second bit line transistor, the third bit line transistor, and the fifth bit line transistor are PMOS; the fourth bit line transistor, the sixth bit line transistor, and the seventh bit line transistor are NMOS. Optionally, in the nonvolatile flash memory, the nonvolatile flash memory further comprises a verification controller, wherein the verification controller is used for controlling the storage state of the bit line buffer. Optionally, in the nonvolatile flash memory, the verification controller includes a first verification transistor, a second verification transistor, and a third verification transistor; The drain electrode of the first verification transistor is connected with the source electrode of the sixth bit line transistor, the source e