CN-122024799-A - Memory control method and device and memory

CN122024799ACN 122024799 ACN122024799 ACN 122024799ACN-122024799-A

Abstract

The disclosure provides a memory control method, a memory control device and a memory, and belongs to the technical field of data storage. The method comprises the steps of responding to the fact that a temperature value of a memory meets a preset temperature condition and the memory is in an erasure preparation state, determining bit lines and word lines to be coupled in the memory, controlling the word lines to be coupled to be applied to a first voltage value, controlling the uncoupled word lines to float, controlling the top select gate to be opened and the bottom select gate to be closed, performing at least one bit line coupling operation, controlling the bit lines to be coupled to be applied to a second voltage value and the uncoupled bit lines to be applied to a third voltage value when a first preset duration threshold is achieved, controlling the bit lines to be coupled to be applied to the third voltage value and the uncoupled bit lines to be applied to the second voltage value until a second preset duration threshold is achieved, and responding to the fact that the preset times are achieved, performing erasure operation on the memory, and improving performance of the memory.

Inventors

YE JIANGLIN
LIN ZIZENG
YANG WENYUAN
LU YU
Jin Haoni
YANG XIUXIA
LU XI
BU ERLONG

Assignees

兆易创新科技集团股份有限公司

Dates

Publication Date: 20260512
Application Date: 20241112

Claims (12)

1. A memory control method, comprising: Determining bit lines and word lines to be coupled in a memory in response to a temperature value of the memory meeting a preset temperature condition and the memory being in an erasure ready state, wherein the bit lines to be coupled in the memory comprise uncoupled bit lines and uncoupled bit lines, and the word lines to be coupled in the memory comprise uncoupled word lines and uncoupled word lines; controlling the word line to be coupled to be applied to a first voltage value, controlling the uncoupled word line to float, controlling the top select gate to be opened and the bottom select gate to be closed; The method comprises the steps of performing bit line coupling operation at least once, wherein each bit line coupling operation comprises the steps of controlling the bit line to be coupled to a second voltage value and the uncoupled bit line to be coupled to a third voltage value, wherein the second voltage value is larger than the third voltage value; And executing erasing operation on the memory in response to the execution times of the bit line coupling operation reach the preset times.
2. The method of claim 1, wherein the determining the bit line and word line to be coupled in the memory comprises: determining a first preset number of continuous or discontinuous bit lines as the bit lines to be coupled, and determining the first preset number of bit lines which are not selected as the bit lines to be coupled as the non-coupled bit lines; And determining a second preset number of word lines close to the top selection gate drain electrode in a storage block of the memory as the word lines to be coupled, and determining other word lines in the storage block as the uncoupled word lines.
3. The method according to claim 1, wherein the method further comprises: Determining a coupling parameter of the word lines to be coupled according to a state parameter of an erase/write operation of the memory, the coupling parameter including at least one of a number of the word lines to be coupled and a first voltage value applied to the word lines to be coupled; The method comprises the steps of erasing the memory, wherein the erasing/writing operation of the memory comprises the erasing operation of the memory, the state parameter of the erasing operation comprises the erasing pulse number, or the erasing/writing operation of the memory comprises the programming operation of the memory, and the state parameter of the programming operation comprises the programming pulse number.
4. A method according to claim 3, wherein the coupling parameters include the number of word lines to be coupled; wherein the determining the bit line and the word line to be coupled in the memory comprises: determining the number of word lines to be coupled as a third preset number in response to the state parameter of the erasing/writing operation of the memory meeting a first preset condition; And determining the number of word lines to be coupled as a fourth preset number in response to the state parameter of the erasing/writing operation of the memory meeting a second preset condition, wherein the fourth preset number is larger than the third preset number.
5. A method according to claim 3, wherein when the coupling parameter comprises a first voltage value applied to the word line to be coupled, the determining the coupling parameter of the word line to be coupled according to the state parameter of the erase/write operation of the memory comprises: determining a first voltage value applied to the word line to be coupled as a first preset voltage value in response to a state parameter of an erase/write operation of the memory satisfying a first preset condition; In response to a status parameter of an erase/write operation of the memory satisfying a second preset condition, determining a first voltage value applied to the word line to be coupled as a second preset voltage value, wherein the second preset voltage value is greater than the first preset voltage value.
6. A method according to claim 4 or 5, characterized in that the method comprises: Determining that a state parameter of an erase/write operation of the memory meets the first preset condition in response to the number of erase pulses being greater than or equal to a first preset erase pulse threshold and less than a second preset erase pulse threshold, or the number of program pulses being less than or equal to a first preset program pulse threshold and greater than a second preset program pulse threshold; Determining that a state parameter of an erase/write operation of the memory satisfies the second preset condition in response to the number of erase pulses being greater than the second preset erase pulse threshold or the number of program pulses being less than the first preset program pulse threshold; the first preset erase pulse threshold is less than the second preset erase pulse threshold, and the first preset program pulse threshold is greater than the second preset program pulse threshold.
7. The method according to claim 4 or 5, characterized in that the method further comprises: in response to a state parameter of an erase/write operation of the memory not satisfying the first preset condition and not satisfying the second preset condition, the bit line coupling operation is not performed.
8. The method of claim 1, wherein the first voltage value comprises voltage values of a plurality of different voltage gradients.
9. The method of claim 1, wherein the first or second predetermined time period threshold is between 20 μs and 300 μs.
10. The method of claim 1, wherein the temperature value of the memory meeting a predetermined temperature condition comprises determining that the temperature value of the memory meets the predetermined temperature condition if the temperature value of the memory is less than or equal to the predetermined temperature value.
11. A memory control apparatus, comprising: the device comprises a coupled line determining module, a first memory and a second memory, wherein the coupled line determining module is used for determining bit lines and word lines to be coupled in the memory in response to the fact that the temperature value of the memory meets a preset temperature condition and the memory is in an erasure preparation state, the bit lines to be coupled in the memory comprise uncoupled bit lines and bit lines to be coupled, and the word lines to be coupled in the memory comprise uncoupled word lines and uncoupled word lines; the word line coupling module is used for controlling the word line to be coupled to be applied to a first voltage value, controlling the uncoupled word line to float, controlling the top select gate to be opened and the bottom select gate to be closed; the bit line coupling module is used for executing at least one bit line coupling operation, wherein each bit line coupling operation comprises the steps of controlling the bit line to be coupled to be applied to a second voltage value and the uncoupled bit line to be applied to a third voltage value, wherein the second voltage value is larger than the third voltage value; and the erasing execution module is used for executing erasing operation on the memory in response to the execution times of the bit line coupling operation reaching the preset times.
12. A memory comprising one or more memory blocks, wherein each of the memory blocks comprises two or more pages therein, and further comprising memory control means configured to perform the memory control method of any of claims 1-10.

Description

Memory control method and device and memory Technical Field The disclosure relates to the technical field of data storage, and in particular relates to a memory control method, a memory control device and a memory. Background Nonvolatile memory is an important way to save data because the stored data is not lost due to power failure. In order to verify the correctness of the memory read operation, it is necessary to precisely control the threshold voltage of the reference voltage of the memory to be tested. The nonvolatile flash memory includes NOR flash memory and NAND flash memory, wherein the NAND flash memory can realize high storage density, and has fast writing and erasing speeds and wide application range because of being capable of providing higher cell density. In the related art, when a NAND flash operates at a low temperature, a device current decreases, in order to ensure a conductive state of a non-selected word line during a program operation or a read operation, a higher Vpass or Vread is generally required, the higher Vpass causes more serious disturbance disturb at the low temperature and causes a read operation error, the larger Vpass causes rapid degradation of the device as the erasing frequency increases, the threshold voltage Vt of the device further moves forward and expands, and deterioration of the cycle stability performance of the device at the low temperature is caused, and a memory control method capable of solving the problem of good low temperature cycle stability at a higher gate voltage is needed. Disclosure of Invention The present disclosure provides a memory control method, apparatus, and memory, which at least partially overcome the problem of degradation of low temperature cycle stability caused by the higher gate voltage provided in the related art. Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure. According to one aspect of the disclosure, a memory control method is provided, which comprises the steps of responding to the fact that a temperature value of a memory meets a preset temperature condition and the memory is in an erasure preparation state, determining that a bit line to be coupled and a word line in the memory are included, wherein the bit line to be coupled includes a non-coupled bit line and a bit line to be coupled, the word line to be coupled in the memory includes the word line to be coupled and the non-coupled word line, controlling the word line to be coupled to be applied to a first voltage value, controlling the non-coupled word line to float, controlling a top select gate to be opened and a bottom select gate to be closed, performing at least one bit line coupling operation, wherein each bit line coupling operation comprises the steps of controlling the bit line to be coupled to be applied to a second voltage value and the non-coupled bit line to be applied to a third voltage value, the second voltage value is larger than the third voltage value, responding to the fact that the duration of performing the bit line coupling operation reaches a first preset duration, controlling the bit line to be coupled to be applied to the third voltage value and the non-coupled to be applied to the second voltage value, and performing the bit line to be coupled reaches the preset duration of time, and performing the bit line coupling operation reaches the preset duration of time to reach the erasure threshold. In one embodiment of the disclosure, the determining the bit lines and word lines to be coupled in the memory includes determining a first preset number of continuous or discontinuous bit lines as the bit lines to be coupled, determining the first preset number of bit lines not selected as the bit lines to be coupled as the bit lines to be uncoupled, determining a second preset number of word lines near the top select gate drain terminal in a memory block of the memory as the word lines to be coupled, and determining other word lines in the memory block as the word lines to be uncoupled. In one embodiment of the present disclosure, the method further comprises determining a coupling parameter of the word lines to be coupled according to a state parameter of an erase/write operation of the memory, the coupling parameter comprising at least one of a number of the word lines to be coupled and a first voltage value applied to the word lines to be coupled, wherein the erase/write operation of the memory comprises an erase operation of the memory, the state parameter of the erase operation comprises a number of erase pulses, or the erase/write operation of the memory comprises a program operation of the memory, the state parameter of the program operation comprises a number of program pulses. In one embodiment of the disclosure, the coupling parameter includes the number of word lines to be coupled, wherein the determining the bit lines and