CN-122024800-A - Memory operation method, memory and memory system

Abstract

The disclosure provides an operation method of a memory, the memory and a memory system, relates to the technical field of memories, and aims to solve the problem of how to shorten programming time. The method includes the steps of executing first program verification operation for a plurality of memory cells of a memory for a plurality of times to obtain a plurality of memory cells of 1 st programming state to i th programming state, i is a positive integer, judging whether to execute first program verification operation of the next programming state or not based on whether a first verification result reaches a first preset value in the first program verification operation, and the first verification result comprises the number of the memory cells of the current programming state. And executing a second program verification operation on the memory cell in the n programming state to obtain a second verification result of the memory cell in the n programming state, wherein n is a positive integer. And if the second verification result of the memory cell in the n programming state is greater than or equal to a second preset value, executing a second programming verification operation on the memory cell in the n+1 programming state, wherein the second preset value is different from the first preset value.

Inventors

• DENG JIALIANG
• LI BO

Assignees

• 长江存储科技有限责任公司

Dates

Publication Date

20260512

Application Date

20230630

Claims (20)

1. 1. A method of operating a memory, the method comprising: performing a first programming operation on a plurality of memory cells of the memory, comprising: Programming the plurality of memory cells to i programming states, i being a positive integer; Performing a first program verification operation on the memory cell of the mth programming state to obtain a first verification result of the memory cell of the mth programming state, m being a positive integer, and Performing the first program verify operation on the memory cells of the (m+1) -th program state in response to the first verify result being greater than or equal to a first preset value, and Performing a second programming operation on a plurality of memory cells of the memory, comprising: Performing a second program verify operation on the memory cells of the n-th programming state to obtain a second verify result of the memory cells of the n-th programming state, n being a positive integer, and Responding to the second verification result being greater than or equal to a second preset value, and executing the second programming verification operation on the memory cell in the n+1th programming state; wherein the second preset value is different from the first preset value.
2. 2. The method of operation of claim 1, wherein the performing a second program verify operation on the n-th programmed state of memory cells, prior to obtaining a second verify result for the n-th programmed state of memory cells, further comprises: And acquiring a pre-verification result of the memory cell of the n programming state based on the verification voltage of the second programming verification operation.
3. 3. The method of operation of claim 2, wherein the second verify result includes a number of memory cells in an n-th programming state, the second preset value being greater than the first preset value.
4. 4. The method of operation of claim 2, wherein the second verification result includes a number of memory cells of an n-th programming state other than a number of memory cells corresponding to the pre-verification result, the second preset value being less than the first preset value.
5. 5. The method of operation of claim 1, wherein programming the plurality of memory cells to the i programming states further comprises: performing the first program verify operation on the memory cell of the mth programming state in response to the first verify result of the memory cell of the mth programming state being less than the first preset value, and And responding to the first verification result obtained by executing the first program verification operation on the memory cell in the highest programming state to obtain a plurality of memory cells from the 1 st programming state to the i-th programming state, wherein the first verification result is larger than or equal to the first preset value.
6. 6. The method of operation of claim 1, wherein the first programming operation and the second programming operation further comprise applying a plurality of programming pulses and a plurality of verify pulses to word lines to which the plurality of memory cells are coupled.
7. 7. The method of operation of claim 6, wherein a step size of the plurality of programming pulses of the first programming operation is greater than a step size of the plurality of programming pulses of the second programming operation.
8. 8. The method of operation of claim 6, wherein a number of the plurality of verify pulses of the first programming operation is less than a number of the plurality of verify pulses of the second programming operation.
9. 9. The method of operation of claim 1, wherein the method further comprises: And responding to the second verification result of the memory cell in the n programming state is smaller than the second preset value, and executing the second programming verification operation on the memory cell in the n programming state.
10. 10. The method of operation of claim 1, wherein the method further comprises: Acquiring a first number of times of the first program verification operation, and obtaining the first preset value according to the first number of times; And obtaining a second number of times of the second program verification operation, and obtaining the second preset value according to the second number of times.
11. 11. A memory, the memory comprising: A memory cell array including a plurality of memory cells; Peripheral circuitry coupled to the array of memory cells, the peripheral circuitry configured to: performing a first programming operation on a plurality of memory cells of the memory, comprising: Programming the plurality of memory cells to i programming states, i being a positive integer; Performing a first program verification operation on the memory cell of the mth programming state to obtain a first verification result of the memory cell of the mth programming state, m being a positive integer, and Performing the first program verify operation on the memory cells of the (m+1) -th program state in response to the first verify result being greater than or equal to a first preset value, and Performing a second programming operation on a plurality of memory cells of the memory, comprising: Performing a second program verify operation on the memory cells of the n-th programming state to obtain a second verify result of the memory cells of the n-th programming state, n being a positive integer, and Responding to the second verification result being greater than or equal to a second preset value, and executing the second programming verification operation on the memory cell in the n+1th programming state; wherein the second preset value is different from the first preset value.
12. 12. The memory of claim 11, wherein the peripheral circuitry is further configured to: And acquiring a pre-verification result of the memory cell of the n programming state based on the verification voltage of the second programming verification operation.
13. 13. The memory of claim 12, wherein the second verify result includes a number of memory cells in an n-th programming state, the second preset value being greater than the first preset value.
14. 14. The memory of claim 12, wherein the second verification result includes a number of memory cells of an n-th programming state other than a number of memory cells corresponding to the pre-verification result, the second preset value being less than the first preset value.
15. 15. The memory of claim 11, wherein the peripheral circuitry is further configured to: performing the first program verify operation on the memory cell of the mth programming state in response to the first verify result of the memory cell of the mth programming state being less than the first preset value, and And responding to the first verification result obtained by executing the first program verification operation on the memory cell in the highest programming state to obtain a plurality of memory cells from the 1 st programming state to the i-th programming state, wherein the first verification result is larger than or equal to the first preset value.
16. 16. The memory of claim 11 wherein the first programming operation and the second programming operation further comprise applying a plurality of programming pulses and a plurality of verify pulses to word lines to which the plurality of memory cells are coupled.
17. 17. The memory of claim 16, wherein a step size of the plurality of programming pulses of the first programming operation is greater than a step size of the plurality of programming pulses of the second programming operation.
18. 18. The memory of claim 16, wherein a number of the plurality of verify pulses of the first programming operation is less than a number of the plurality of verify pulses of the second programming operation.
19. 19. The memory of claim 11, wherein the peripheral circuitry is further configured to: And responding to the second verification result of the memory cell in the n programming state being smaller than the second preset value, and executing the second programming verification operation on the memory cell in the n programming state.
20. 20. The memory of claim 11, wherein the peripheral circuitry is further configured to: Acquiring a first number of times of the first program verification operation, and obtaining the first preset value according to the first number of times; And obtaining a second number of times of the second program verification operation, and obtaining the second preset value according to the second number of times.

Description

Memory operation method, memory and memory system The application relates to a method for operating a memory, a memory and a memory system, which are divisional applications of Chinese patent application with the application date of 2023, 6, 30, and the application number 2023108026174. Technical Field The disclosure relates to the technical field of memories, and in particular relates to an operation method of a memory, the memory and a memory system. Background NAND flash memory is a nonvolatile memory technology, namely, the NAND flash memory can still store data after power failure, and has the advantages of low memory cost, high memory capacity and the like. The conventional NAND flash memory chip is usually programmed by a progressive step pulse programming (INCREMENTAL STEP pulse programming, ISPP) method, and the memory cell is programmed by using a programming voltage which is increased gradually, and each programming pulse is followed by a corresponding verification pulse to check whether the threshold voltage of the memory cell reaches a target value. As the number of bits stored in a memory cell increases, so does the time required for programming. The number of times the program pulse is applied and the number of times the program verify operation is performed are important factors in determining the program time. Therefore, how to shorten the programming time on the premise of ensuring the programming quality becomes a problem to be solved urgently. Disclosure of Invention Embodiments of the present disclosure provide a memory operation method, a memory, and a memory system, which aim to solve the problem of how to shorten the programming time. In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions. In a first aspect, a method for operating a memory is provided, the method including performing a plurality of first program verify operations on a plurality of memory cells of the memory to obtain a plurality of memory cells of a 1 st program state to an i-th program state, i being a positive integer, determining whether to perform a first program verify operation of a next program state based on whether a first verify result reaches a first preset value in the first program verify operation, the first verify result including a number of memory cells of a current program state. And executing a second program verification operation on the memory cell in the n programming state to obtain a second verification result of the memory cell in the n programming state, wherein n is a positive integer. And if the second verification result of the memory cell in the n programming state is greater than or equal to a second preset value, executing a second programming verification operation on the memory cell in the n+1 programming state, wherein the second preset value is different from the first preset value. The operation method of the memory provided by the above embodiment of the present disclosure adopts a two-step programming method including coarse programming and fine programming. Wherein, in the rough programming, based on the first preset value, judging whether to perform the first program verification operation of the next programming state, and in the fine programming, based on the second preset value, judging whether to perform the second program verification operation of the next programming state. Compared with the same preset value adopted by coarse programming and fine programming, the operation method of the memory provided by the embodiment of the application adopts different preset values in the coarse programming and the fine programming, so that the influence of the coarse programming on the fine programming can be reduced, the verification times of the fine programming can be reduced, and the programming time can be shortened. In some embodiments, before performing the second program verify operation on the memory cell of the nth program state to obtain the second verify result of the memory cell of the nth program state, the method further includes obtaining a pre-verify result of the memory cell of the nth program state based on a verify voltage of the second program verify operation. In these embodiments, the pre-verification result is the number of memory cells that have reached the n-th programmed state after the coarse programming is completed, and the pre-verification result can be understood as the influence of the coarse programming on the fine programming, and the value of the second preset value in the fine programming can be adjusted based on the pre-verification result, so that the verification operation of the fine programming is reduced, and the programming time is reduced. In some embodiments, the second verification result includes a number of memory cells in an n-th programming state, and the second preset value is greater than the first preset value. In these embodiments, if the second verification resul