CN-122024801-A - Shift register unit and driving method thereof, grid driving circuit and display device

Abstract

A shift register unit, a driving method thereof, a grid driving circuit and a display device are provided, and belong to the technical field of display. In the shift register unit, the register circuit can transmit signals with different potentials to the control node in different time periods under the control of signals such as input signals, clock signals and the like, so that the transmission circuit and the output circuit can both output signals with different potentials through the connected output ends in different time periods under the control of the potential of the control node. Therefore, the shift register unit can be a mixed circuit of a P-type transistor and an N-type transistor, and has simple structure and better output reliability.

Inventors

• WANG ZHU
• SHI LING
• FANG FEI

Assignees

• 京东方科技集团股份有限公司
• 成都京东方光电科技有限公司
• 北京京东方技术开发有限公司

Dates

Publication Date

20260512

Application Date

20241112

Claims (16)

1. 1. A shift register unit, characterized in that the shift register unit comprises: The register circuit is respectively connected with the input end, the first clock end, the second clock end, the first power end, the second power end and the control node, and is used for responding to an input signal provided by the input end, a first clock signal provided by the first clock end and a second clock signal provided by the second clock end, controlling the on-off of the first power end and the control node, controlling the on-off of the second power end and the control node, and conducting the first power end and the second power end with the control node in different time periods; The transmission circuit is respectively connected with the control node, the third clock end, the third power end and the cascade output end, and is used for responding to the potential of the control node, controlling the on-off of the third clock end and the cascade output end and controlling the on-off of the third power end and the cascade output end so as to output cascade signals to other cascade stage shift register units through the cascade output end, wherein the third clock end and the third power end are respectively conducted with the cascade output end in different time periods; The output circuit is respectively connected with the control node, the fourth clock end, the fourth power end and the scanning output end, and is used for responding to the potential of the control node, controlling the on-off of the fourth clock end and the scanning output end, and controlling the on-off of the fourth power end and the scanning output end so as to output scanning signals to pixels in the display panel through the scanning output end, and the fourth clock end and the fourth power end are respectively conducted with the scanning output end in different time periods.
2. 2. The shift register unit according to claim 1, wherein the register circuit includes: The first register sub-circuit is respectively connected with the input end, the first clock end, the first power end, the second power end, a first intermediate node, a second intermediate node and a third intermediate node, and is used for controlling the on-off of the first power end and the first intermediate node, controlling the on-off of the first power end and the second intermediate node and controlling the on-off of the second power end and the third intermediate node in response to the input signal and in response to the first clock signal; The second register sub-circuit is respectively connected with the input end, the first clock end, the second clock end, the first intermediate node, the second intermediate node, the third intermediate node and the control node, and is used for responding to the first clock signal to control the on-off of the first intermediate node and the control node, responding to the second clock signal to control the on-off of the second intermediate node and the control node, and responding to the input signal to control the on-off of the third intermediate node and the control node.
3. 3. The shift register cell as claimed in claim 2, wherein the first register sub-circuit comprises a first transistor, a second transistor and a third transistor, wherein the first transistor and the second transistor are one-type transistors, and the third transistor is two-type transistors; The grid electrode of the first transistor is connected with the input end, the first pole of the first transistor is connected with the first power supply end, and the second pole of the first transistor is connected with the first intermediate node; the grid electrode of the second transistor is connected with the input end, the first electrode of the second transistor is connected with the first power end, and the second electrode of the second transistor is connected with the second intermediate node; The gate of the third transistor is connected to the first clock terminal, the first pole of the third transistor is connected to the second power supply terminal, and the second pole of the third transistor is connected to the third intermediate node.
4. 4. The shift register cell as claimed in claim 2, wherein the second register sub-circuit comprises a fourth transistor, a fifth transistor and a sixth transistor, and wherein the fifth transistor is a one-type transistor and the fourth transistor and the sixth transistor are two-type transistors; the grid electrode of the fourth transistor is connected with the first clock end, the first electrode of the fourth transistor is connected with the first intermediate node, and the second electrode of the fourth transistor is connected with the control node; the grid electrode of the fifth transistor is connected with the second clock end, the first electrode of the fifth transistor is connected with the second intermediate node, and the second electrode of the fifth transistor is connected with the control node; the gate of the sixth transistor is connected to the input terminal, the first pole of the sixth transistor is connected to the third intermediate node, and the second pole of the sixth transistor is connected to the control node.
5. 5. The shift register cell as claimed in any one of claims 1 to 4, wherein the transfer circuit comprises a seventh transistor and an eighth transistor, and wherein the seventh transistor is a one-type transistor and the eighth transistor is a two-type transistor; the grid electrode of the seventh transistor is connected with the control node, the first electrode of the seventh transistor is connected with the third power supply end, and the second electrode of the seventh transistor is connected with the cascade output end; the grid electrode of the eighth transistor is connected with the control node, the first electrode of the eighth transistor is connected with the third clock end, and the second electrode of the eighth transistor is connected with the cascade output end.
6. 6. The shift register cell as claimed in any one of claims 1 to 4, wherein the output circuit comprises a ninth transistor and a tenth transistor, and wherein the ninth transistor is a one-type transistor and the tenth transistor is a two-type transistor; A grid electrode of the ninth transistor is connected with the control node, a first electrode of the ninth transistor is connected with the fourth power supply end, and a second electrode of the ninth transistor is connected with the scanning output end; the gate of the tenth transistor is connected to the control node, the first pole of the tenth transistor is connected to the fourth clock terminal, and the second pole of the tenth transistor is connected to the scan output terminal.
7. 7. The shift register unit as claimed in any one of claims 1 to 4, further comprising: The signal enhancement circuit is connected between the output circuit and the scanning output end, is also respectively connected with a fifth power end and a sixth power end, and is used for enhancing the scanning signal output by the output circuit based on a fifth power signal provided by the fifth power end and a sixth power signal provided by the sixth power end and then transmitting the scanning signal to the scanning output end.
8. 8. The shift register cell as claimed in claim 7, wherein the signal enhancing circuit comprises a cascade of an even number of inverters; Each of the inverters includes an eleventh transistor and a twelfth transistor connected in series between the fifth power supply terminal and the sixth power supply terminal, and the eleventh transistor is a one-type transistor and the twelfth transistor is a two-type transistor.
9. 9. The shift register cell as claimed in claim 7, wherein in the even number of inverters, a potential of a fifth power supply signal supplied from a fifth power supply terminal to which a last inverter is connected is equal to or less than a potential of a fifth power supply signal supplied from a fifth power supply terminal to which other inverters than the last inverter are connected, and a potential of a sixth power supply signal supplied from a sixth power supply terminal to which the last inverter is connected is equal to or more than a potential of a sixth power supply signal supplied from a sixth power supply terminal to which the other inverters are connected, and an output terminal of the last inverter is directly connected to the scan output terminal.
10. 10. The shift register cell of claim 9, wherein a fifth power supply terminal to which the third power supply terminal, the fourth power supply terminal, and the other inverters are connected is common to the first power supply terminal; And/or, a sixth power supply terminal connected with the other inverters is shared with the second power supply terminal; And/or, the third clock terminal is shared with the first clock terminal.
11. 11. The shift register cell of claim 3 or 4, wherein in the shift register cell, the first type transistor is an N-type transistor and the second type transistor is a P-type transistor.
12. 12. The shift register cell as claimed in claim 1-4, wherein the shift register cell further comprises a capacitor connected between the second power supply terminal and the control node.
13. 13. A method of driving a shift register unit according to any one of claims 1 to 12, the method comprising: The first stage, the register circuit responds to the input signal provided by the input end, the first clock signal provided by the first clock end and the second clock signal provided by the second clock end, the first power end is controlled to be conducted with the control node, the second power end is controlled to be disconnected with the control node, the transmission circuit responds to the potential of the control node, the third power end is controlled to be conducted with the cascade output end, the third clock end is controlled to be disconnected with the cascade output end, the output circuit responds to the potential of the control node, the fourth power end is controlled to be conducted with the scanning output end, the fourth clock end is controlled to be disconnected with the scanning output end, so that the third power signal provided by the third power end is transmitted to the cascade output end, and the fourth power signal provided by the fourth power end is transmitted to the scanning output end; And in a second stage, the register circuit responds to the input signals, the first clock signal and the second clock signal, the first power end is controlled to be disconnected from the control node, the second power end is controlled to be conducted with the control node, the transmission circuit responds to the potential of the control node, the third power end is controlled to be disconnected from the cascade output end, the third clock end is controlled to be conducted with the cascade output end, the output circuit responds to the potential of the control node, the fourth power end is controlled to be disconnected from the scanning output end, the fourth clock end is controlled to be conducted with the scanning output end, so that the third clock signal provided by the third clock end is transmitted to the cascade output end, and the fourth clock signal provided by the fourth clock end is transmitted to the scanning output end.
14. 14. A gate driving circuit is characterized by comprising a plurality of cascaded shift register units according to any one of claims 1 to 12, wherein the cascade output end of each stage of shift register unit is connected with the input ends of the shift register units of other stages of cascade; And, the cascade-connected multiple shift register units comprise multiple groups of shift register units, each group of shift register units comprises at least two shift register units in cascade connection; the at least two shift register units are alternately connected with at least two fourth clock terminals in turn in a one-to-one correspondence, and the plurality of groups of shift register units share the at least two fourth clock terminals.
15. 15. The gate driving circuit according to claim 14, wherein each group of the shift register units includes two shift register units, and the two shift register units are alternately connected in turn in one-to-one correspondence with two fourth clock terminals.
16. 16. A display device comprising a display panel and the gate drive circuit according to claim 14 or 15, wherein the display panel comprises a plurality of pixels; the grid driving circuit is connected with the pixels through the scanning output ends and is used for transmitting grid driving signals to the pixels so as to drive the pixels to emit light.

Description

Shift register unit and driving method thereof, grid driving circuit and display device Technical Field The present application relates to the field of display technologies, and in particular, to a shift register unit, a driving method thereof, a gate driving circuit, and a display device. Background The gate driving circuit is a circuit for transmitting gate driving signals to a plurality of rows of pixels in a display panel to drive the plurality of rows of pixels to emit light. In addition, with the development of display technology, in view of the design of a narrow frame, an array substrate row driving (GOA) technology is mostly adopted to integrate a gate driving circuit on a display panel. Accordingly, the gate driving circuit may also be referred to as a GOA circuit. Currently, a GOA circuit generally includes a plurality of shift register units (also referred to as GOA units) in cascade connection, where the plurality of GOA units are connected to a plurality of rows of pixels in a one-to-one correspondence manner, and are configured to output gate driving signals to the plurality of rows of pixels row by row so as to drive the plurality of rows of pixels to emit light. But the current GOA cell structure is relatively complex. Disclosure of Invention A shift register unit, a driving method thereof, a gate driving circuit and a display device are provided, which can solve the problem of complex structure of GOA units in the related art. The technical scheme is as follows: in one aspect, there is provided a shift register unit including: The register circuit is respectively connected with the input end, the first clock end, the second clock end, the first power end, the second power end and the control node, and is used for responding to an input signal provided by the input end, a first clock signal provided by the first clock end and a second clock signal provided by the second clock end, controlling the on-off of the first power end and the control node, controlling the on-off of the second power end and the control node, and conducting the first power end and the second power end with the control node in different time periods; The transmission circuit is respectively connected with the control node, the third clock end, the third power end and the cascade output end, and is used for responding to the potential of the control node, controlling the on-off of the third clock end and the cascade output end and controlling the on-off of the third power end and the cascade output end so as to output cascade signals to other cascade stage shift register units through the cascade output end, wherein the third clock end and the third power end are respectively conducted with the cascade output end in different time periods; The output circuit is respectively connected with the control node, the fourth clock end, the fourth power end and the scanning output end, and is used for responding to the potential of the control node, controlling the on-off of the fourth clock end and the scanning output end, and controlling the on-off of the fourth power end and the scanning output end so as to output scanning signals to pixels in the display panel through the scanning output end, and the fourth clock end and the fourth power end are respectively conducted with the scanning output end in different time periods. Optionally, the register circuit includes: The first register sub-circuit is respectively connected with the input end, the first clock end, the first power end, the second power end, a first intermediate node, a second intermediate node and a third intermediate node, and is used for controlling the on-off of the first power end and the first intermediate node, controlling the on-off of the first power end and the second intermediate node and controlling the on-off of the second power end and the third intermediate node in response to the input signal and in response to the first clock signal; The second register sub-circuit is respectively connected with the input end, the first clock end, the second clock end, the first intermediate node, the second intermediate node, the third intermediate node and the control node, and is used for responding to the first clock signal to control the on-off of the first intermediate node and the control node, responding to the second clock signal to control the on-off of the second intermediate node and the control node, and responding to the input signal to control the on-off of the third intermediate node and the control node. The first register sub-circuit comprises a first transistor, a second transistor and a third transistor, wherein the first transistor and the second transistor are one-type transistors, and the third transistor is two-type transistors; The grid electrode of the first transistor is connected with the input end, the first pole of the first transistor is connected with the first power supply end, and the second pole of the first transistor is connec