CN-122024802-A - Calibration method, integrated circuit and memory device including integrated circuit

Abstract

A calibration method, an integrated circuit, and a memory device are provided. The calibration method includes outputting a second data clock obtained by compensating a first data clock based on a calibration signal and a first voltage, outputting a first pulse based on the first data clock and the second data clock, updating a control signal based on a reference voltage and the first pulse, the reference voltage being generated based on the control signal, outputting a third data clock obtained by compensating the first data clock based on the calibration signal and a second voltage smaller than the first voltage, outputting a second pulse based on the first data clock and the third data clock, and updating the calibration signal according to the reference voltage and the second pulse generated based on the updated control signal.

Inventors

• An Zhemin
• LI CAIYU
• Jin Jihan
• WEN DAZHI

Assignees

• 三星电子株式会社

Dates

Publication Date

20260512

Application Date

20250829

Priority Date

20241111

Claims (20)

1. 1. A calibration method, comprising: Outputting a second data clock obtained by compensating the first data clock based on the calibration signal and the first voltage; outputting a first pulse based on the first data clock and the second data clock; Updating a control signal based on a reference voltage and the first pulse, wherein the reference voltage is generated based on the control signal; outputting a third data clock obtained by compensating the first data clock based on the calibration signal and a second voltage smaller than the first voltage; outputting a second pulse based on the first data clock and the third data clock, and The calibration signal is updated according to the second pulse and a reference voltage generated based on the updated control signal.
2. 2. The method of calibration according to claim 1, Wherein outputting the first pulse based on the first data clock and the second data clock comprises: the first pulse is output by performing an and operation on the inversion of the second data clock and the first data clock.
3. 3. The method of calibration according to claim 1, Wherein outputting the first pulse based on the first data clock and the second data clock comprises: the first pulse at a logic high voltage is output during a first period in which the first data clock is at a logic high voltage and the second data clock is at a logic low voltage.
4. 4. The method of calibration according to claim 1, Wherein updating the control signal based on the reference voltage and the first pulse comprises: The control signal is updated such that the magnitude of the reference voltage generated based on the updated control signal is equal to or greater than the duty cycle of the first pulse.
5. 5. The method of calibration according to claim 1, Wherein updating the control signal based on the reference voltage and the first pulse comprises: The control signal is updated by repeatedly adding a first offset to the control signal until the magnitude of a reference voltage generated based on the control signal is equal to or greater than the duty cycle of the first pulse.
6. 6. The method of calibration according to claim 1, Wherein updating the calibration signal based on the reference voltage and the second pulse comprises: The calibration signal is updated such that the amplitude of the reference voltage generated based on the updated control signal is equal to or greater than the duty cycle of the second pulse.
7. 7. The method of calibration according to claim 1, Wherein updating the calibration signal based on the reference voltage and the second pulse comprises: The calibration signal is updated by repeatedly adding a second offset to the calibration signal until the amplitude of the reference voltage is greater than or equal to the duty cycle of the second pulse.
8. 8. The method of calibration according to claim 1, Wherein updating the calibration signal according to the second pulse and a reference voltage generated based on the updated control signal comprises: The calibration signal is updated by repeatedly adding a second offset to the calibration signal until the updated calibration signal has a preset maximum value.
9. 9. The method of calibration according to claim 1, Wherein the reference voltage is generated by adjusting a resistance ratio of the first resistor and the second resistor of the reference voltage generating circuit according to the control signal.
10. 10. The calibration method of claim 1, further comprising: initializing the calibration signal and the control signal.
11. 11. An integrated circuit, comprising: A data clock path circuit configured to receive a first voltage, a first data clock, and a calibration signal, and configured to compensate for a delay of the first data clock using the first voltage according to the calibration signal to output a second data clock; A comparison circuit configured to output a first pulse based on the first data clock and the second data clock; A reference voltage generating circuit configured to receive a control signal and configured to output a reference voltage according to the control signal, and A duty cycle monitor configured to compare the magnitude of the reference voltage with the duty cycle of the first pulse, and configured to output a first comparison signal corresponding to a comparison result of the magnitude of the reference voltage with the duty cycle of the first pulse.
12. 12. The integrated circuit of claim 11, Wherein the comparison circuit is configured to perform an and operation on the inversion of the second data clock and the first data clock to output the first pulse.
13. 13. The integrated circuit of claim 11, Wherein the comparison circuit is configured to output the first pulse at a logic high voltage during a first time interval in which the first data clock is at a logic high voltage and the second data clock is at a logic low voltage.
14. 14. The integrated circuit of claim 11, Wherein the reference voltage generation circuit includes a first resistor and a second resistor, and is configured to adjust a resistance ratio of the first resistor and the second resistor according to the control signal to output the reference voltage.
15. 15. The integrated circuit of claim 14, The reference voltage generating circuit adjusts the size of the first resistor according to the control signal so as to adjust the resistance ratio of the first resistor and the second resistor.
16. 16. The integrated circuit of claim 11, further comprising: And a control logic circuit configured to update the control signal based on the first comparison signal.
17. 17. The integrated circuit of claim 16, Wherein the control logic is configured to update the control signal such that the magnitude of the reference voltage generated based on the updated control signal is equal to or greater than the duty cycle of the first pulse.
18. 18. The integrated circuit of claim 16, Wherein the control logic is configured to update the control signal by repeatedly adding a first offset to the control signal until the logic value of the first comparison signal changes.
19. 19. The integrated circuit of claim 16, Wherein the control logic is configured to update the control signal by repeatedly adding a first offset to the control signal until the magnitude of the reference voltage generated based on the updated control signal is greater than or equal to the duty cycle of the first pulse.
20. 20. A memory device, comprising: A memory cell array configured to store data; A data clock path circuit configured to output a second data clock based on a first data clock and a first voltage, and configured to output a third data clock based on the first data clock and a second voltage smaller than the first voltage; A calibration circuit configured to determine a calibration signal based on the first data clock, the second data clock, and the third data clock, and Control logic configured to provide the calibration signal to the data clock path circuit, Wherein the data clock path circuit is configured to output a fourth data clock based on the first data clock and the calibration signal, an Wherein the control logic circuit is configured to write data to the array of memory cells using the fourth data clock.

Description

Calibration method, integrated circuit and memory device including integrated circuit Cross Reference to Related Applications The present application claims priority and ownership rights obtained from korean patent application No.10-2024-0158979 filed at the korean intellectual property office on 11 months 2024, 11, the entire contents of which are incorporated herein by reference. Technical Field The invention relates to a calibration method, an integrated circuit and a memory device including the integrated circuit. Background The memory device receives signals such as commands, addresses, and data from outside the memory and processes the signals. In receiving and storing data from the outside and outputting the data to the outside, the memory device samples the data according to a data clock. At this time, a delay may occur in the data clock on the data clock path (i.e., the path through which the data clock is transmitted inside the memory device). The power supply voltage required for operation can be supplied to the memory device from the outside. However, the amplitude of the received power supply voltage may not be kept constant due to reasons such as noise. The magnitude of the delay that occurs in the data clock may vary depending on the fluctuations in the supply voltage received by the data clock path. Thus, there is a compensation circuit on the data clock path, which can compensate for a difference in the magnitude of delay that occurs in the data clock depending on the fluctuation of the power supply voltage. However, there may be a difference in the compensation degree of each memory device due to such reasons as the difference in sensitivity of each memory device to the power supply voltage. Disclosure of Invention Aspects of the present invention provide a calibration method. Aspects of the invention also provide an integrated circuit capable of performing the calibration method. Aspects of the present invention also provide a memory device employing an integrated circuit capable of performing the calibration method. According to some embodiments of the present disclosure, there is provided a calibration method including outputting a second data clock obtained by compensating a first data clock based on a calibration signal and a first voltage, outputting a first pulse based on the first data clock and the second data clock, updating a control signal based on a reference voltage and the first pulse, the reference voltage being generated based on the control signal, outputting a third data clock obtained by compensating the first data clock based on the calibration signal and a second voltage smaller than the first voltage, outputting a second pulse based on the first data clock and the third data clock, and updating the calibration signal according to the reference voltage and the second pulse generated based on the updated control signal. According to some embodiments of the present disclosure, there is provided an integrated circuit including a data clock path circuit configured to receive a first voltage, a first data clock, and a calibration signal, and configured to compensate for a delay of the first data clock using the first voltage according to the calibration signal to output a second data clock, a comparison circuit configured to output a first pulse based on the first data clock and the second data clock, a reference voltage generation circuit configured to receive a control signal, and configured to output a reference voltage according to the control signal, and a duty cycle monitor configured to compare an amplitude of the reference voltage with a duty cycle of the first pulse, and configured to output a first comparison signal corresponding to a comparison result of the amplitude of the reference voltage with the duty cycle of the first pulse. According to some embodiments of the present disclosure, there is provided a memory device including a memory cell array configured to store data, a data clock path circuit configured to output a second data clock based on a first data clock and a first voltage and configured to output a third data clock based on the first data clock and a second voltage smaller than the first voltage, a calibration circuit configured to determine a calibration signal based on the first data clock, the second data clock, and the third data clock, and a control logic circuit configured to provide the calibration signal to the data clock path circuit, wherein the data clock path circuit is configured to output a fourth data clock based on the first data clock and the calibration signal, and the control logic circuit is configured to write data to the memory cell array using the fourth data clock. However, aspects of the invention are not limited to the aspects set forth herein. The above and other aspects of the present invention will become more apparent to those of ordinary skill in the art to which the present invention pertains by referencing the de