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CN-122024803-A - Multi-block embedded flash memory test circuit and test method thereof

CN122024803ACN 122024803 ACN122024803 ACN 122024803ACN-122024803-A

Abstract

The invention belongs to the technical field of semiconductor memory testing, and particularly relates to a multi-block embedded flash memory testing circuit and a testing method thereof. The serial-parallel interface testing device comprises an SPI main control module, a data conversion module, a time sequence control module, a Flash selection module and a test command, wherein the SPI main control module is used for realizing serial-parallel receiving and sending of data based on an SPI interface protocol and external testing equipment so as to generate a command and data required by testing, the data conversion module is used for completing the adaption of an input-output data format so as to ensure the correct transmission of the data between a testing circuit and a Flash block, the time sequence control module is used for generating a control signal required by the Flash block according to testing requirements, and the Flash selection module is used for driving the selected Flash block to execute programming, erasing and reading operations according to the control signal output by the time sequence control module and the testing command output by the data conversion module. The invention solves the problems of low test efficiency, inaccurate time sequence control and the like in the prior art.

Inventors

  • GUO JIAN

Assignees

  • 中国电子科技集团公司第五十八研究所

Dates

Publication Date
20260512
Application Date
20260129

Claims (10)

  1. 1. A multi-block embedded flash memory test circuit, comprising: the SPI main control module is communicated with external test equipment based on an SPI interface protocol to realize serial and parallel receiving and sending of data, so that commands and data required by testing are generated; The data conversion module is used for completing the adaptation of the input and output data format so as to ensure the correct transmission of data between the test circuit and the Flash block; The time sequence control module is used for generating control signals required by the Flash block according to the test requirements; And the Flash selection module is used for driving the selected Flash block to execute programming, erasing and reading operations according to the control signal output by the time sequence control module and the test command output by the data conversion module.
  2. 2. The multi-block embedded flash memory test circuit of claim 1, wherein the SPI master control module is internally provided with a synchronous circuit, external test equipment inputs signals according to an SPI interface protocol, the test circuit selects serial or parallel data transmission for the input signals and obtains input synchronous data after processing the input signals by the synchronous circuit, the synchronous circuit comprises a first trigger and a second trigger, reset ends of the first trigger and the second trigger are connected with a reset signal rstn, an input end D of the first trigger is connected with a spi_din [3:0] data input, an input end D of the second trigger is connected with din_d data output by an output end Q of the first trigger, an output end Q of the second trigger outputs syn_ tdin [3:0] synchronous data, and clock ends CLK of the first trigger and the second trigger are connected with an external clock CLK.
  3. 3. The multi-block embedded Flash memory test circuit of claim 2, wherein the data conversion module is embedded with a read-write-erase state machine to obtain correct test commands and data, and is capable of adapting to Flash IP with data bit width of less than 144 bits.
  4. 4. The embedded Flash memory test circuit of claim 3, wherein the data conversion module analyzes the test command according to the input synchronous data to obtain the address and number of the corresponding operation, splits 144bit data into 364 bit data through a block transmission strategy when inputting the programming operation command, transmits the 36 bit data in parallel through the SPI main control module or splits the 144bit data into 144 1bit data, transmits the 144bit data through the SPI main control module in series, reassembles the 144bit data into 144bit data in the data conversion module after the transmission is completed, and transmits the 144bit data into an input data bus flash_din of Flash IP.
  5. 5. The multi-block embedded Flash memory test circuit as claimed in claim 3, wherein when a read operation command is input, the timing control module inputs a corresponding read timing signal to the Flash IP, sends the read 144-bit output data flash_dout to the data conversion module, splits the 144-bit data into 36 4-bit data or 144 1-bit data through a block transmission strategy, and transmits the 36-bit data or 144-bit data to an external 4-line PAD or 1-line PAD through the SPI master control module.
  6. 6. The multi-block embedded Flash memory test circuit of claim 1, wherein the timing control module freely adapts timing parameter requirements of control signals between 20mhz and 100mhz according to an input clock frequency to meet test requirements of Flash IP.
  7. 7. The multi-block embedded Flash memory test circuit of claim 1, wherein the Flash selection module selects to read, program, erase any one of the 8 Flash blocks, or to read, program, erase the 8 Flash blocks together, respectively.
  8. 8. The multi-block embedded flash memory test circuit of claim 3, wherein the read-write-erase state machine further comprises a state jump flow of: The default reset value of the state machine is in an idle state, when the chip select signal ceb of the Flash IP is pulled down, the state machine jumps into a FLASH_SEL state, if the SPI main control module continues to output a corresponding Flash block select instruction, the state machine jumps into an instruction state, the SPI main control module continues to output a corresponding operation instruction, the state machine jumps into a low-eight-bit address state, and continues to jump into a high-eight-bit address state; If the programming and reading instructions are input previously, the state machine jumps to a number state, the SPI main control module is required to continuously input the number required to be programmed and read, the state machine jumps to a programming or reading state respectively, and when the number required to be programmed or read is 0, the programming or reading operation is ended, and the state machine jumps to an idle state; If the previously input erase command is either sector erase or full-slice erase, the state machine jumps directly from the address state to the erase state, and when the erase is finished, the state machine jumps to the idle state, and the new operation command is repeatedly input to repeatedly perform the read-write erase operation on the Flash IP.
  9. 9. The multi-block embedded Flash memory test circuit of claim 1, wherein the test circuit and Flash memory to be tested can be integrated into the same chip.
  10. 10. A method for testing a multi-block embedded flash memory, which adopts the multi-block embedded flash memory testing circuit according to any one of claims 1 to 9, comprising: Firstly, preparing to test, selecting a serial or parallel input mode, inputting a specified test instruction sequence through an SPI interface protocol, and performing read-write-erase operation on a Flash IP; If a programming operation instruction is sent out, the programming address and the programming operation number are continuously input, programming data are continuously input, and the test circuit continuously judges that the programming operation is finished until the programming number is 0; If a reading operation instruction is sent out, the next step is to continuously input a reading address and the number of the reading operation, then the test circuit reads the data of the corresponding address to the off-chip external test equipment until the reading number is 0, and the reading operation is ended; if an erasing operation instruction is sent, the next step is to input an erasing address, and then the test circuit directly performs erasing operation until the erasing operation is finished; and repeatedly inputting a new operation instruction, and performing read-write erasing operation on the Flash IP through the test circuit.

Description

Multi-block embedded flash memory test circuit and test method thereof Technical Field The invention belongs to the technical field of semiconductor memory testing, and particularly relates to a multi-block embedded Flash memory testing circuit and a testing method thereof, which are suitable for functional verification, performance testing and mass production screening of an embedded Flash memory. Background Along with the continuous progress of semiconductor technology, embedded flash memories are widely applied to integrated circuits such as Microcontrollers (MCUs) and system-on-a-chip (socs) to meet the demands of code storage and data storage. In some mature middle-high end process platforms, embedded storage has the combined advantages of cost and performance. However, the manufacturing process of the embedded flash memory is complex, and factors such as process deviation and device aging affect the read-write speed, reliability and service life of the memory cell. In the chip mass production stage, high-efficiency and accurate testing means are required to ensure the yield and quality of the product. The existing test circuit has the disadvantages of complex structure, poor compatibility, inflexible time sequence control, incapability of adjusting an input test frequency range, single data transmission and signal conditioning modes, and improvement of test efficiency and coverage rate. Therefore, it is necessary to design an embedded flash memory test circuit with simple structure, simple operation, high timing controllability and high test coverage rate, which is a counting problem to be solved in the art. Disclosure of Invention The invention aims to provide a multi-block embedded flash memory test circuit and a test method thereof, which are used for solving the problems of low test efficiency, inaccurate time sequence control and the like in the prior art. In order to solve the above technical problems, the present invention provides a multi-block embedded flash memory test circuit, comprising: the SPI main control module is communicated with external test equipment based on an SPI interface protocol to realize serial and parallel receiving and sending of data, so that commands and data required by testing are generated; The data conversion module is used for completing the adaptation of the input and output data format so as to ensure the correct transmission of data between the test circuit and the Flash block; The time sequence control module is used for generating control signals required by the Flash block according to the test requirements; And the Flash selection module is used for driving the selected Flash block to execute programming, erasing and reading operations according to the control signal output by the time sequence control module and the test command output by the data conversion module. Preferably, the SPI master control module is internally provided with a synchronous circuit, external test equipment inputs signals according to an SPI interface protocol, the test circuit selects serial or parallel data transmission for the input signals and obtains input synchronous data after the input signals are processed by the synchronous circuit, the synchronous circuit comprises a first trigger and a second trigger, a reset end of the first trigger and a reset end of the second trigger are connected with a reset signal rstn, an input end D of the first trigger is connected with a spe_din3:0 data input, an input end D of the second trigger is connected with din_d data output by an output end Q of the first trigger, an output end Q of the second trigger outputs syn_ tdin [3:0] synchronous data, and a clock end CLK of the first trigger and a clock end CLK of the second trigger are connected with an external clock sclk. Preferably, the data conversion module is internally provided with a read-write-erase state machine to obtain correct test commands and data, and can adapt to Flash IP with the data bit width of less than 144 bits. Preferably, the data conversion module analyzes the test instruction according to the input synchronous data to obtain the address and the number of the corresponding operation, splits the 144bit data into 36 4bit data through a block transmission strategy when inputting the programming operation instruction, transmits the 36 bit data in parallel through the SPI main control module or splits the 144bit data into 144 1bit data through the SPI main control module, and transmits the 144bit data into 144bit data in the data conversion module after the transmission is completed in series, and then transmits the 144bit data into an input data bus flash_din of the Flash IP. Preferably, when a read operation instruction is input, the timing control module inputs a corresponding read timing signal to the Flash IP, sends the read 144-bit output data flash_dout to the data conversion module, splits the 144-bit data into 36 4-bit data or 144 1-bit data through a block transm