CN-122024804-A - Method, device and system for testing nonvolatile memory and nonvolatile memory

CN122024804ACN 122024804 ACN122024804 ACN 122024804ACN-122024804-A

Abstract

The application relates to the technical field of data storage, and discloses a testing method for a nonvolatile memory, which comprises the steps of loading first control information from a nonvolatile memory array by utilizing a logic selection unit, so as to switch on a testing control logic unit and switch off an SPI control logic unit based on the first control information; the method comprises the steps of controlling the multiplexing external communication port to be connected through the test control logic unit to obtain test control information from the external test equipment so as to control the nonvolatile memory to enter an engineering mode, obtaining a first test signal from the external test equipment through the multiplexing external communication port, sending the first test signal to the nonvolatile memory array through the test control logic unit so as to obtain a first test result, and sending the first test result to the external test equipment through the multiplexing external communication port. The method and the device realize the test of the nonvolatile memory array by using part of external communication ports, and improve the test efficiency. The application also discloses a testing device and a testing system for the nonvolatile memory, and the nonvolatile memory.

Inventors

LIU JIAQI
XU XIANG
HUANG JINHUANG

Assignees

北京紫光青藤微系统有限公司

Dates

Publication Date: 20260512
Application Date: 20260114

Claims (10)

1. The test method for the nonvolatile memory is characterized in that the nonvolatile memory comprises a nonvolatile memory array, a logic selection unit, a test control logic unit, an SPI control logic unit and an external communication port, wherein the external communication port controlled to be connected by the test control logic unit is multiplexed with a part of the external communication port controlled to be connected by the SPI control logic unit, and the test method comprises the following steps: Loading first control information from the nonvolatile memory array by using the logic selection unit to switch on the test control logic unit and switch off the SPI control logic unit based on the first control information; Acquiring test control information from external test equipment through a multiplexing external communication port controlled to be connected by a test control logic unit, and controlling the nonvolatile memory to enter an engineering mode by utilizing the test control information; After the nonvolatile memory enters an engineering mode, a first test signal is acquired from external test equipment through a multiplexing external communication port, the first test signal is sent to the nonvolatile memory array by utilizing a test control logic unit to acquire a first test result, and the first test result is sent to the external test equipment through the multiplexing external communication port.
2. The method of testing of claim 1, wherein transmitting the first test signal to the nonvolatile memory array to obtain the first test result comprises: acquiring a first test result reading signal from an external test device via a multiplexed external communication port; Transmitting the first test result reading signal to the nonvolatile memory array to acquire a first test result for executing the first test signal from the nonvolatile memory array; Or alternatively Acquiring a first test state read signal from an external test device via a multiplexed external communication port; transmitting the first test state read signal to the nonvolatile memory array to acquire a first execution state for executing the first test signal from the nonvolatile memory array; after the first execution state is sent to the external test equipment, a first test result reading signal is obtained from the external test equipment through the multiplexing external communication port; The first test result read signal is sent to the nonvolatile memory array to obtain a first test result from the nonvolatile memory array to execute the first test signal.
3. The test method of claim 1 or 2, wherein the first test signal comprises one or more of an analog calibration command, a write command, and an erase command.
4. The method of testing of claim 1, wherein the method of testing further comprises: acquiring second control information from the external test equipment through the multiplexing external communication port, so that the logic selection unit turns off the test control logic unit and turns on the SPI control logic unit based on the second control information; Acquiring second test signals from external test equipment through all external communication ports controlled to be connected by the SPI control logic unit, and performing SPI control logic test based on the second test signals to acquire second test results; the second test result is sent to the external test device via all external communication ports.
5. The method of claim 4, wherein storing the second control information in the nonvolatile memory array overrides the original first control information to generate new first control information.
6. The test method of claim 1, wherein the test interface protocol of the test control logic unit employs an I2C interface protocol.
7. A test apparatus for a nonvolatile memory comprising a processor and a memory storing program instructions, wherein the processor is configured, when executing the program instructions, to perform the test method for a nonvolatile memory as claimed in any one of claims 1 to 6.
8. The nonvolatile memory is characterized by comprising a nonvolatile memory array, a logic selection unit, a test control logic unit, an SPI control logic unit and an external communication port, wherein the external communication port controlled to be connected by the test control logic unit multiplexes part of the external communication ports controlled to be connected by the SPI control logic unit, and the nonvolatile memory comprises the following components: the nonvolatile memory array stores first control information; the logic selection unit is connected with the nonvolatile storage array, the test control logic unit and the SPI control logic unit and is configured to load first control information from the nonvolatile storage array so as to switch on the test control logic unit and switch off the SPI control logic unit based on the first control information; The test control logic unit is connected with the nonvolatile memory array and the multiplexing external communication interface and is configured to acquire test control information from external test equipment through the multiplexing external communication port so as to control the nonvolatile memory to enter an engineering mode by using the test control information, acquire a first test signal from the external test equipment through the multiplexing external communication port after the nonvolatile memory enters the engineering mode, send the first test signal to the nonvolatile memory array so as to acquire a first test result, and send the first test result to the external test equipment through the multiplexing external communication port.
9. The non-volatile memory of claim 8, wherein the memory is configured to store, in the memory, The external communication ports controlled to be connected by the SPI control logic unit comprise an SPI input port, an SPI output port, an SPI chip selection signal port and an SPI clock signal port; The multiplexing external communication ports controlled to be connected by the test control logic unit comprise multiplexing data ports and multiplexing clock signal ports, wherein the multiplexing data ports are multiplexed with SPI input ports, and the multiplexing clock signal ports are multiplexed with SPI clock signal ports.
10. A test system for a nonvolatile memory, comprising: at least one nonvolatile memory as in claim 9; and the external test equipment is connected with the nonvolatile memory through the test pin card.

Description

Method, device and system for testing nonvolatile memory and nonvolatile memory Technical Field The present application relates to the field of data storage technologies, and for example, to a method, an apparatus and a system for testing a nonvolatile memory, and a nonvolatile memory. Background A nonvolatile memory is a memory chip capable of holding stored data after power failure, which communicates with external devices through interfaces, and different interfaces determine the communication speed, complexity, cost and application scenarios thereof. The nonvolatile memory has a plurality of interface types, and is suitable for different communication protocols and different numbers of signal ports. The SPI interface is a universal serial input/output interface, and generally includes at least four ports of a chip select signal cs#, an input signal si#, an output signal so#, and a clock signal sclk#, and has more signal ports in a scene with a higher transmission rate requirement, such as IO0 (si#), IO1 (so#), IO2, IO3, and IO4, IO5, IO6, and IO7 in a four-wire scene. Nonvolatile memory testing typically involves two parts, the first part being testing of the nonvolatile memory array and the second part being testing of the control logic and input output ports, where testing of the nonvolatile memory array primarily tests each memory cell. In this scenario, if the nonvolatile memory adopts the SPI interface, all the multiple signal ports of the interface need to be led out one by one for testing, which results in lower testing efficiency and high testing cost. It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art. Disclosure of Invention The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows. The embodiment of the disclosure provides a test method, a test device, a test system and a test control logic unit for a nonvolatile memory, wherein the test control logic unit is added into the nonvolatile memory provided with an SPI communication logic unit, when the nonvolatile memory array is tested, only part of external communication ports are led out for testing, so that the testing efficiency is improved, and the testing cost is reduced. In some embodiments, the nonvolatile memory comprises a nonvolatile memory array, a logic selection unit, a test control logic unit, an SPI control logic unit and an external communication port, wherein the external communication port controlled to be connected by the test control logic unit multiplexes a part of the external communication port controlled to be connected by the SPI control logic unit, and the test method for the nonvolatile memory comprises the following steps: Loading first control information from the nonvolatile memory array by using the logic selection unit to switch on the test control logic unit and switch off the SPI control logic unit based on the first control information; Acquiring test control information from external test equipment through a multiplexing external communication port controlled to be connected by a test control logic unit, and controlling the nonvolatile memory to enter an engineering mode by utilizing the test control information; After the nonvolatile memory enters an engineering mode, a first test signal is acquired from external test equipment through a multiplexing external communication port, the first test signal is sent to the nonvolatile memory array by utilizing a test control logic unit to acquire a first test result, and the first test result is sent to the external test equipment through the multiplexing external communication port. In some embodiments, a test apparatus for a nonvolatile memory includes a processor and a memory storing program instructions, wherein the processor is configured to perform the test method for a nonvolatile memory described above when the program instructions are executed. In some embodiments, the nonvolatile memory includes a nonvolatile memory array, a logic selection unit, a test control logic unit, an SPI control logic unit, and an external communication port, wherein the external communication port controlled by the test control logic unit is multiplexed with a portion of the external communication ports controlled by the SPI control logic unit, wherein: the nonvolatile memory array stores first control information; the logic selection unit is connected with the nonvolatile storage array, the test control logic unit and the SPI control logic unit and is configured to