CN-122024808-A - Storage chip aging defect analysis system based on electric test data

CN122024808ACN 122024808 ACN122024808 ACN 122024808ACN-122024808-A

Abstract

The invention discloses a storage chip aging defect analysis system based on electrical test data, which relates to the technical field of storage chip aging tests and is used for solving the problem of inaccurate aging defect identification; the invention establishes a limit working point, an error count and a margin reference baseline for chips in the same batch by constructing a unified electric test data frame and an array, block, row, column and page coordinate system in the wafer test, finished product test and aging stage. The system compares the unit aging characteristic sequences to generate aging characteristic vectors, divides the storage units into common units, suspicious units and aging high-sensitivity units according to thresholds, identifies defects of maintaining capacity degradation, reading interference sensitivity and erasure cycle sensitivity, forms an aging sensitive unit map, generates stress conditions, test vectors and inserting test frequency combinations based on the map, and combines redundant arrays or redundant blocks to remap and risk classification, so that the screening of potential failure units is realized and the reliability of a chip is improved.

Inventors

CHEN SHI
HU WANGAN
CHENG HAO
ZHANG FENGFENG
ZHENG YOUJUN
QIAN HAI

Assignees

深圳市宸悦存储电子科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260203

Claims (10)

1. The system is characterized by comprising an electrical measurement acquisition module, an address alignment module, a characteristic generation module, a sensitive identification module and a strategy updating module, wherein the modules are connected through signals; The electrical test acquisition module is used for acquiring chip electrical test results in wafer test, finished product test and aging test, uniformly coding chip identification, test stage, test conditions, address information and electrical test indexes, and generating an electrical test data frame; The address alignment module is used for mapping addresses in the electric test data frame into array, block, row, column or page coordinates according to the memory array structure, sequencing the electric test data in the test stage according to the chip identification and the unit coordinates according to the time and stress sequence, and constructing a memory unit aging characteristic sequence; the feature generation module is used for calculating limit working points, error sequences and margins for the storage units based on the aging feature sequences, and comparing the limit working points, the error sequences and the margins with reference base lines of chips in the same batch to generate aging feature vectors; The sensitive identification module is used for carrying out multi-index judgment on the aging characteristic vector according to a judgment rule, dividing the storage unit into a common unit, a suspicious unit and an aging high-sensitivity unit, summarizing the sensitivity level and the defect type according to the coordinates of an array, a block, a row, a column or a page, and generating an aging sensitive unit map; And the strategy updating module is used for setting stress conditions, test vectors and inserting test frequency combinations according to the sensitivity level and the position of the aging sensitive unit map, generating test and screening strategies, writing the electric test results obtained by executing the strategies into the electric test data frame, and updating the aging analysis results.
2. The system for analyzing the aging defect of the memory chip based on the electrical test data of claim 1, wherein the functional result and the electrical parameters generated by the wafer probe test are collected in a wafer test stage, the chip identification, the test stage identification, the test condition and the wafer coordinate information are recorded, and an electrical test data frame is written; Acquiring functional results and electrical parameters generated by packaging finished product chip-level testing in a finished product testing stage, recording chip identification, testing stage identification, testing conditions and packaging identification information, and writing an electrical testing data frame; the method comprises the steps of collecting functional results and electrical parameters generated by a pre-aging test, an aging process insertion test and an aging ending test in an aging test stage, recording chip identification, test stage identification, test conditions and aging time information, and writing an electrical test data frame; And calibrating the time stamps corresponding to the wafer test, the finished product test and the burn-in test, adopting a unified time reference to represent the test occurrence time, combining the test occurrence time with the batch identification, and storing the test occurrence time and the test occurrence time into a time field and a batch field in an electrical test data frame.
3. The system for analyzing aging defects of a memory chip based on electrical test data as set forth in claim 2, wherein the address alignment module comprises: Establishing a coordinate system comprising an array number, a block number, a row number, a column number and a page number, and describing the space position of a storage unit in a memory chip; Analyzing and converting the logical address generated by the test program into an array, block, row, column or page coordinate in a coordinate system; aggregating records belonging to the same storage unit in the electric test data frame by taking the chip identification and the storage unit coordinates as index keys to form an electric test record set of the corresponding storage unit; and sequencing the electric test record set according to the time field, setting a stress intensity sequence according to the voltage, the temperature and the working frequency in the test condition, and arranging the records under the time sequence and the stress intensity sequence to construct an aging characteristic sequence of the storage unit.
4. The system for analyzing aging defects of a memory chip based on electrical test data according to claim 3, wherein the electrical test data of the same production lot is counted according to test stages and test conditions to obtain a lot reference baseline reflecting typical levels and variation ranges under normal aging conditions in each test stage and each test condition; for each storage unit, calculating the variation of the limit working point in each test stage and each test condition in the aging characteristic sequence, recording the test stage and the test condition in which the error appears for the first time, and calculating the reduction amplitude and the reduction rate of the margin in the test sequence; Comparing the variable quantity, the first occurrence stage information and the margin change index with the corresponding batch reference base line to obtain a deviation amplitude and a deviation direction; and combining the limit working point change feature, the error occurrence feature, the margin change feature and the deviation feature to form an aging feature vector of the storage unit.
5. The system for analyzing aging defects of a memory chip based on electrical test data according to claim 4, wherein the five indexes of limiting operating point variation amplitude, error first occurrence stage, error type combination, margin reduction rate and deviation degree relative to a batch reference baseline in the aging characteristic vector are jointly judged; when the change amplitude of the limit working point is larger than a first threshold value, the deviation degree is larger than a second threshold value, and the first error occurrence stage is earlier than a preset stage, marking the corresponding storage unit as an aging high-sensitivity unit; When the variation amplitude of the limit working point is between the first threshold value and the third threshold value and the deviation degree is larger than the fourth threshold value, marking the corresponding storage unit as a suspicious unit; For a storage unit, the change amplitude and the deviation degree of the limit working point of which are in a preset normal range and the first occurrence stage of errors is later than a preset stage, marking the storage unit as a common unit; And writing classification results of the common unit, the suspicious unit and the aging high-sensitivity unit into a sensitivity level field in the aging high-sensitivity unit map.
6. The system for analyzing aging defects of a memory chip based on electrical test data according to claim 5, wherein the defect type judgment is performed according to the occurrence position and the occurrence sequence of errors in the hold test, the read disturb test and the erase-write cycle test; Marking a retention capacity degradation type on a memory cell in which an error occurs only in a retention test and an error does not occur in a read disturb test and an erase cycle test; Marking the read disturb sensitive type on memory cells that are only subject to errors in read disturb tests and are not subject to errors in retention tests and erase cycle tests; marking the erase-write cycle sensitive type on the memory cells where errors occur only in the erase-write cycle test and where no errors occur in the hold test and the read disturb test; When the aging sensitive unit map is generated, the sensitive level field and the defect type field are recorded for each storage unit at the same time, so that the aging sensitive unit map simultaneously displays the sensitive level distribution and three aging defect type distributions on an array, block, row, column or page coordinate level.
7. The system for analyzing the aging defect of the memory chip based on the electrical test data according to claim 1, wherein a strategy mapping relation is respectively established for a common unit, a suspicious unit and an aging high-sensitivity unit in an aging sensitive unit map, the common unit is mapped to a test strategy using standard stress conditions, standard test vector combinations and basic test frequency, the suspicious unit is mapped to a test strategy using increased voltage or temperature, increased boundary voltage scanning points and increased test frequency, the aging high-sensitivity unit is mapped to a test strategy using higher stress conditions, increased holding test sequences and read interference test sequences and shortened test intervals, and test and screening strategy entries containing stress condition parameters, test vector identifications and test cycle parameters are generated for each memory unit according to the mapping result.
8. The system for analyzing aging defects of a memory chip based on electrical test data as set forth in claim 1, wherein the policy updating module further comprises: According to the space distribution condition of the aging high-sensitivity units in the aging sensitive unit map, counting the number and the centralized position of the aging high-sensitivity units in each storage block, when the number of the aging high-sensitivity units in the storage block exceeds a preset restoration threshold, selecting idle resources in a redundant row, a redundant column or a redundant block resource set, generating a remapping target list of a corresponding storage block, sending the remapping target list to a restoration control unit to execute address remapping operation, carrying out electric test verification on a remapping area after the remapping operation is finished, and writing electric test results before and after restoration into an electric test data frame for updating a batch reference base line and restoration strategy parameters.
9. The system for analyzing the aging defects of the memory chip based on the electrical test data according to claim 1, wherein an aging risk grade score is calculated for each chip according to a sensitivity grade field and a defect type field in an aging sensitive unit map, the aging risk grade score is calculated based on the number of aging high sensitive units, the distribution proportion of the sensitive units in a key array and a defect type combined structure, the chips are classified into a high-reliability grade, a standard grade and a degradation grade according to the aging risk grade score, a reliable application scene and strict aging conditions are allocated for the high-reliability grade chips, a common application scene and standard aging conditions are allocated for the standard grade chips, constraint application scenes and reinforcing screening conditions are allocated for the degradation grade chips, and a grade classification result is written into a chip factory configuration record.
10. The system for analyzing aging defects of a memory chip based on electrical test data as set forth in claim 1, wherein the sensitive identification module and the policy updating module further comprise: Recording the corresponding relation among an aging sensitive unit map, an actual aging failure record and a repair result record in the continuous operation process of the production batch, and forming an aging performance history record set; evaluating coverage degree and misjudgment condition of batch reference base line and sensitivity level threshold setting on actual aging failure based on aging performance history record set; when the coverage degree is lower than a preset target or the misjudgment condition exceeds a preset upper limit, adjusting a statistical window of a batch reference baseline, a sensitivity level threshold value, and a stress condition parameter range and an interpolation period parameter range in strategy mapping; and writing the updated batch reference baseline, the sensitivity level threshold and the strategy mapping parameters into the system configuration after the parameter adjustment is completed.

Description

Storage chip aging defect analysis system based on electric test data Technical Field The invention relates to the technical field of aging test of memory chips, in particular to a memory chip aging defect analysis system based on electrical test data. Background In the memory chip manufacturing and reliability verification scene, a staged electric test flow of a wafer test and a finished product test matched with a high-temperature aging test is generally adopted, and programs such as reading and writing, maintaining, erasing and writing cycles are executed through a probe station, a finished product tester and an aging test station to perform function screening and parameter screening on the chip. Engineering personnel usually judge the process stability and ageing risk according to single limit condition test results, simple statistical reports and overall yield indexes, and block-level or chip-level fuse repair and grading shipment strategies are assisted to meet the requirements of different application scenes on reliability, and the process is widely applied under the conditions of traditional capacity and lower storage density. However, in actual production, wafer testing, finished product testing and aging testing are often independently completed by different platforms, test data formats are not uniform, address representation modes are inconsistent, testing conditions and time references are dispersed, it is difficult to reconstruct complete stress history and performance evolution tracks on a single storage unit level, analysis work is stopped at a chip level or block level statistics level, aging defect identification generally depends on an overall failure rate index, different aging modes such as holding capacity degradation, read interference sensitivity and erasure cycle sensitivity cannot be distinguished carefully, a mechanism for linking space distribution characteristics with redundancy repair strategies, aging condition adjustment and factory grading strategies is also lacking, the problem that potential aging sensitive units are covered up, excessive screening causes resource waste or aging strategies are difficult to optimize adaptively along with batch characteristics easily occurs, and reliability requirements of high-density multi-level storage chips in a whole life cycle are difficult to meet. Disclosure of Invention In order to overcome the defects in the prior art, the following scheme is provided to solve the problem of inaccurate identification of the aging defects in the prior art. In order to achieve the above purpose, the present invention provides the following technical solutions: the system comprises an electrical measurement acquisition module, an address alignment module, a characteristic generation module, a sensitive identification module and a strategy updating module, wherein the modules are connected through signals; The electrical test acquisition module is used for acquiring chip electrical test results in wafer test, finished product test and aging test, uniformly coding chip identification, test stage, test conditions, address information and electrical test indexes, and generating an electrical test data frame; The address alignment module is used for mapping addresses in the electric test data frame into array, block, row, column or page coordinates according to the memory array structure, sequencing the electric test data in the test stage according to the chip identification and the unit coordinates according to the time and stress sequence, and constructing a memory unit aging characteristic sequence; the feature generation module is used for calculating limit working points, error sequences and margins for the storage units based on the aging feature sequences, and comparing the limit working points, the error sequences and the margins with reference base lines of chips in the same batch to generate aging feature vectors; The sensitive identification module is used for carrying out multi-index judgment on the aging characteristic vector according to a judgment rule, dividing the storage unit into a common unit, a suspicious unit and an aging high-sensitivity unit, summarizing the sensitivity level and the defect type according to the coordinates of an array, a block, a row, a column or a page, and generating an aging sensitive unit map; And the strategy updating module is used for setting stress conditions, test vectors and inserting test frequency combinations according to the sensitivity level and the position of the aging sensitive unit map, generating test and screening strategies, writing the electric test results obtained by executing the strategies into the electric test data frame, and updating the aging analysis results. Further, functional results and electrical parameters generated by the wafer probe test are collected in a wafer test stage, chip identification, test stage identification, test conditions and wafer coordinate information are re