CN-122026683-A - Quasi-resonant flyback converter and light load management circuit thereof

CN122026683ACN 122026683 ACN122026683 ACN 122026683ACN-122026683-A

Abstract

The application provides a quasi-resonant flyback converter and a light load management circuit thereof. The light load management circuit comprises a first comparator, a valley detection circuit, a valley locking circuit, a valley overtime circuit, an SR trigger, a turn-off time control circuit and a turn-off time control circuit, wherein when a set input end receives a zero-crossing detection signal or a valley overtime signal, the SR trigger outputs a control signal to turn on a switch tube, the input end is connected to a feedback pin, the output end is respectively connected with the valley overtime circuit and an enabling end of the SR trigger, the turn-off time control circuit is used for providing corresponding turn-off time based on feedback voltage, and the SR trigger is enabled after the turn-off time. The turn-off time control circuit provides a first turn-off time when the feedback voltage is not lower than the predetermined voltage, and provides a second turn-off time when the feedback voltage is lower than the predetermined voltage, and the second turn-off time is longer than the first turn-off time, thereby enabling the output power to smoothly drop when the load is reduced.

Inventors

XU JUNXIANG
GAO HUA
LUO BINGYIN

Assignees

华润微集成电路(无锡)有限公司

Dates

Publication Date: 20260512
Application Date: 20241111

Claims (11)

1. A light load management circuit for a quasi-resonant flyback converter, the quasi-resonant flyback converter including a switching tube for controlling power supply of an input voltage thereof, the light load management circuit comprising: the inverting input end of the first comparator is connected to a feedback pin for receiving feedback voltage, and the non-inverting input end of the first comparator is connected to a sampling pin for receiving sampling voltage; The valley bottom detection circuit is used for detecting the oscillating voltage generated by the quasi-resonant flyback converter after the switching tube is turned off and generating a valley bottom detection signal when the valley bottom of the oscillating voltage is detected; The valley locking circuit is used for counting the valleys of the valley detection signal and sending out a zero-crossing detection signal when the valley count reaches a preset counting threshold value; the valley timeout circuit is used for sending out a valley timeout signal when the time of not detecting the valley bottom reaches the maximum turn-off time threshold value; The set input end of the SR trigger is connected with the valley locking circuit and the valley overtime circuit, the reset input end of the SR trigger is connected with the output end of the first comparator, the output end of the SR trigger is connected to the grid electrode of the switching tube, and when the set input end receives the zero-crossing detection signal or the valley overtime signal, the output end of the SR trigger outputs a control signal to conduct the switching tube; The input end of the turn-off time control circuit is connected to the feedback pin, the output end of the turn-off time control circuit is respectively connected with the valley timeout circuit and the enabling end of the SR trigger, the turn-off time control circuit is used for providing corresponding turn-off time based on the feedback voltage, the SR trigger is enabled after the turn-off time is passed, The turn-off time provided by the turn-off time control circuit is a first turn-off time when the feedback voltage is not lower than a predetermined voltage, and is a second turn-off time when the feedback voltage is lower than the predetermined voltage, and the second turn-off time is longer than the first turn-off time.
2. The light load management circuit of claim 1, wherein the off-time control circuit comprises: A minimum off-time circuit for providing a predetermined minimum off-time; A dead time generating circuit connected between the feedback pin and the minimum off time circuit for providing a corresponding dead time based on the feedback voltage when the feedback voltage is lower than the predetermined voltage, and adding the dead time to the minimum off time provided by the minimum off time circuit to obtain the second off time, Wherein the first off-time provided by the off-time control circuit is equal to the minimum off-time when the feedback voltage is not lower than the predetermined voltage.
3. The light load management circuit of claim 2, wherein the dead time generation circuit comprises a first PMOS tube, a second PMOS tube, a first current source, a second current source, a third current source, a second transmission gate, a second capacitor, a second comparator and a Schmitt trigger, and wherein the first current source and the second current source provide the same current, wherein, The grid electrode of the first PMOS tube is used for receiving the feedback voltage, the source electrode of the first PMOS tube is connected with the input ends of the first current source and the second transmission gate, and the drain electrode of the first PMOS tube is grounded; The upper polar plate of the second capacitor is respectively connected with the output end of the second transmission gate, the third current source and the positive end of the second comparator, and the lower polar plate of the second capacitor is grounded; The enabling end of the second transmission gate is enabled by the inverted signal of the control signal; The grid electrode of the second PMOS tube is used for receiving a second reference voltage, the source electrode of the second PMOS tube is connected with the second current source and the inverting input end of the second comparator, and the drain electrode of the second PMOS tube is grounded; the input end of the Schmitt trigger is connected with the output end of the second comparator, and the output end of the Schmitt trigger is connected to the minimum turn-off time circuit.
4. The light load management circuit of claim 3, wherein the dead time generation circuit further comprises a first inverter and a second inverter, wherein, The output end of the schmitt trigger is connected to the minimum turn-off time circuit through the first inverter and the second inverter.
5. The light load management circuit of claim 2, wherein the minimum off-time circuit comprises a second NMOS transistor, a third NMOS transistor, a fourth current source, a third capacitor, and a third comparator, wherein, The grid electrode of the second NMOS tube is connected with the output end of the dead time generation circuit, and the source electrode of the second NMOS tube is grounded; The grid electrode of the third NMOS tube is used for receiving the control signal, and the source electrode of the third NMOS tube is grounded; The upper polar plate of the third capacitor is respectively connected with the drain electrode of the second NMOS tube, the drain electrode of the third NMOS tube, the fourth current source and the non-inverting input end of the third comparator, and the lower polar plate of the third capacitor is grounded; and the inverting input end of the third comparator is used for receiving a third reference voltage, and the output end of the third comparator is connected with the input end of the valley timeout circuit.
6. The light load management circuit of claim 1, wherein the valley timeout circuit comprises a third inverter, a fourth NMOS transistor, a fifth current source, a fourth capacitor, and a fourth comparator, wherein, The input end of the third inverter is connected with the output end of the turn-off time control circuit; The grid electrode of the third NMOS tube is connected with the output end of the third inverter, and the source electrode of the third NMOS tube is grounded; the upper polar plate of the fourth capacitor is connected with the drain electrode of the third NMOS tube, the fifth current source and the non-inverting input end of the fourth comparator, and the lower polar plate of the fourth capacitor is grounded; the inverting input end of the fourth comparator is used for receiving a fourth reference voltage, and the output end of the fourth comparator is used for outputting the Gu Chaoshi signals.
7. The light load management circuit of claim 1, wherein the valley lock circuit and the valley timeout circuit are connected to a set input of the SR flip-flop through logic gates.
8. The light load management circuit of claim 7, wherein the logic gate circuit comprises a first OR gate and a second OR gate, wherein, The two input ends of the first OR gate respectively receive the zero crossing detection signal and the Gu Chaoshi signal, and the output end of the first OR gate is connected with one input end of the second OR gate; the other input end of the second OR gate is used for receiving the longest switching period limiting signal of the switching tube, and the output end of the second OR gate is connected with the setting input end of the SR trigger.
9. The light load management circuit of any one of claims 1 to 8, further comprising a first transmission gate and a division circuit, wherein, The input end of the first transmission gate is connected with the feedback pin, the output end of the first transmission gate is connected with the input end of the division operation circuit, and the division operation circuit is used for dividing the feedback voltage by a preset proportionality coefficient to reduce the feedback voltage; The output end of the division operation circuit is respectively connected with the inverting input end of the first comparator and the input end of the turn-off time control circuit.
10. The light load management circuit of any one of claims 1-8, further comprising a leading edge blanking circuit connected between the sampling pin and a non-inverting input of the first comparator.
11. A quasi-resonant flyback converter comprising a transformer, a switching tube for controlling the supply of an input voltage of the transformer, and a light load management circuit for a quasi-resonant flyback converter according to any one of claims 1 to 10.

Description

Quasi-resonant flyback converter and light load management circuit thereof Technical Field The application relates to the technical field of converters, in particular to a quasi-resonant flyback converter and a light load management circuit thereof. Background The main characteristic of the Quasi-Resonant (QR) flyback converter is that the switching tube can be turned on at the valley, so that the loss of the switching tube can be effectively reduced. The flyback converter in the Quasi-Resonant (QR, quasi response) mode works, when the flyback converter works under the light load working condition, the switching frequency is controlled by the valley detection signal, the switching frequency is high, so that the loss in the light load mode is high, even if the number of the valleys experienced when the flyback voltage is regulated and controlled to be on according to the feedback voltage, the switching tube can be crossed and conducted in the valley locking mode and the valley overtime mode while the circuit complexity is increased, the jump is generated at the output power point, and the output noise is increased. Disclosure of Invention The embodiment of the application aims to provide a quasi-resonant flyback converter and a light load management circuit thereof, so that output power is smoothly reduced when load is reduced, loss is reduced, and meanwhile, the noise problem generated by power point jump is relieved. One aspect of the application provides a light load management circuit for a quasi-resonant flyback converter. The quasi-resonant flyback converter includes a switching tube for controlling the supply of its input voltage. The light load management circuit comprises a first comparator, a valley bottom detection circuit, a valley bottom locking circuit, a valley timeout circuit, an SR trigger and a turn-off time control circuit. The inverting input terminal of the first comparator is connected to a feedback pin for receiving a feedback voltage, and the non-inverting input terminal is connected to a sampling pin for receiving a sampling voltage. The valley detection circuit is used for detecting oscillating voltage generated by the quasi-resonant flyback converter after the switching tube is turned off and generating a valley detection signal when the valley of the oscillating voltage is detected. The valley locking circuit is used for performing valley counting on the valley detection signals and sending out zero-crossing detection signals when the valley counting reaches a preset counting threshold value. And the valley timeout circuit is used for sending out a valley timeout signal when the time when the valley bottom is not detected reaches the maximum turn-off time threshold value. The set input end of the SR trigger is connected with the valley locking circuit and the valley overtime circuit, the reset input end of the SR trigger is connected with the output end of the first comparator, the output end of the SR trigger is connected to the grid electrode of the switching tube, and when the set input end receives the zero-crossing detection signal or the valley overtime signal, the output end of the SR trigger outputs a control signal to conduct the switching tube. The input end of the turn-off time control circuit is connected to the feedback pin, the output end of the turn-off time control circuit is respectively connected with the valley timeout circuit and the enabling end of the SR trigger, the turn-off time control circuit is used for providing corresponding turn-off time based on the feedback voltage, the SR trigger is enabled after the turn-off time passes, the turn-off time provided by the turn-off time control circuit is first turn-off time when the feedback voltage is not lower than a preset voltage, and the turn-off time provided by the turn-off time control circuit is second turn-off time when the feedback voltage is lower than the preset voltage, and the second turn-off time is longer than the first turn-off time. Further, the off-time control circuit includes a minimum off-time circuit and a dead time generation circuit. The minimum off-time circuit is configured to provide a predetermined minimum off-time. The dead time generation circuit is connected between the feedback pin and the minimum turn-off time circuit and is used for providing corresponding dead time based on the feedback voltage when the feedback voltage is lower than the preset voltage and adding the dead time to the minimum turn-off time provided by the minimum turn-off time circuit so as to obtain the second turn-off time. Wherein the first off-time provided by the off-time control circuit is equal to the minimum off-time when the feedback voltage is not lower than the predetermined voltage. The dead time generation circuit further comprises a first PMOS tube, a second PMOS tube, a first current source, a second current source, a third current source, a second transmission gate, a second capacitor, a second co