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CN-122026695-A - Frequency planning and ADC sampling scheduling method and system for multiple converters

CN122026695ACN 122026695 ACN122026695 ACN 122026695ACN-122026695-A

Abstract

The invention discloses a multi-converter frequency planning and ADC sampling scheduling method and system, wherein the method comprises the steps of obtaining the sampling frequency of each converter in a multi-converter system; the method comprises the steps of calculating the least common multiple of sampling frequencies of all converters, calculating unified time base frequency and unified time base period according to the least common multiple, sampling safety distance time of a multi-converter system, judging whether the unified time base period is larger than or equal to the minimum time interval allowed between any two sampling triggers, if so, distributing sampling trigger offset time for all converters according to the unified time base frequency, and generating an ADC trigger sequence of all converters according to the sampling trigger offset time distributed for all converters. The invention aims to avoid ADC resource conflict caused by sampling coincidence in a multi-converter system, and ensure the certainty and stability of sampling time in the multi-converter system, thereby improving the sampled data quality.

Inventors

  • TANG LONG
  • LUO DERONG
  • XIAO MUXUAN
  • CHEN CHANGXI

Assignees

  • 湖南大学

Dates

Publication Date
20260512
Application Date
20260414

Claims (10)

  1. 1. A method for frequency planning and ADC sampling scheduling of a multi-converter, comprising the steps of: S101, acquiring sampling frequencies of all converters in a multi-converter system; s102, calculating the least common multiple of the sampling frequency of each converter; s103, calculating a unified time base frequency and a unified time base period according to the least common multiple; S104, sampling the safe distance time of the multi-converter system, wherein the safe distance time is the minimum time interval allowed between any two sampling triggers, judging whether the unified time base period is larger than or equal to the safe distance time, if so, jumping to execute the next step, otherwise, judging whether the safe distance time can be reduced, if the safe distance time can be reduced, jumping to the step S104, if not, further judging whether the least common multiple of the sampling frequency of each converter can be reduced, if the least common multiple of the sampling frequency of each converter can be reduced, jumping to the step S103, and if the least common multiple of the sampling frequency of each converter can not be reduced, judging that the system does not meet the requirement, ending and exiting; s105, distributing sampling trigger offset time to each converter according to the unified time base frequency; S106, generating ADC trigger sequences of the converters according to the sampling trigger offset time allocated to the converters.
  2. 2. The multiple converter frequency planning and ADC sampling scheduling method according to claim 1, wherein the function expression for calculating the least common multiple of the sampling frequency of each converter in step S102 is: ; Wherein, the Is the least common multiple of the sampling frequency of each converter, In order to find the function of the least common multiple, ~ Respectively 1 st to 1 st The sampling frequency of the individual converters is chosen, Is the total number of converters in the multi-converter system.
  3. 3. The multiple converter frequency planning and ADC sampling scheduling method according to claim 1, wherein in step S103, the function expression for calculating the unified time-based frequency and the unified time-based period according to the least common multiple is: ; Wherein, the For a uniform time-base period, In order to unify the time-based frequencies, For the total number of converters in a multi-converter system, Is the least common multiple of the sampling frequency of each converter.
  4. 4. The multiple converter frequency planning and ADC sampling scheduling method according to claim 1, wherein the functional expression of the safe distance time of the sampling multiple converter system in step S105 is: ; Wherein, the In order for the safe distance time to be within a safe range, For the ADC conversion time it is time to convert, In order to read the time of the ADC conversion result, Is a safety margin.
  5. 5. The multiple converter frequency planning and ADC sampling scheduling method of claim 4, wherein the time to read the ADC conversion result is a time to read the ADC conversion result by DMA or a time to read the ADC conversion result by CPU.
  6. 6. The multiple converter frequency planning and ADC sampling scheduling method according to claim 1, wherein the function expression for assigning sampling trigger offset times to the respective converters according to the uniform time base frequency in step S105 is: ; Wherein, the Is the first The sampling of the individual converters triggers an offset time, For the index number of the transducer, In order to unify the time-based frequencies, Is the total number of converters in the multi-converter system.
  7. 7. The multiple converter frequency planning and ADC sampling scheduling method of claim 1, wherein the generating the function expression of the ADC trigger sequences of each converter according to the sampling trigger offset time allocated to each converter in step S106 is: ; Wherein, the Is the first The ADC trigger sequences of the individual converters, For the sample point index number of the ADC trigger sequence, Is a negative integer which is a whole number, Is the first The sampling period of the one converter is chosen, Wherein Is the first The sampling frequency of the individual converters is chosen, Is the first The sampling of the individual converters triggers the offset time.
  8. 8. A multiple converter frequency planning and ADC sampling scheduling system comprising a microprocessor and a memory interconnected, wherein the microprocessor is programmed or configured to perform the multiple converter frequency planning and ADC sampling scheduling method of any one of claims 1 to 7.
  9. 9. A computer readable storage medium having stored therein a computer program or instructions, the computer program or instructions being programmed or configured to perform the multi-transducer frequency planning and ADC sampling scheduling method of any one of claims 1 to 7 by a processor.
  10. 10. A computer program product comprising a computer program or instructions programmed or configured to perform the multi-transducer frequency planning and ADC sampling scheduling method of any one of claims 1 to 7 by a processor.

Description

Frequency planning and ADC sampling scheduling method and system for multiple converters Technical Field The invention relates to an electric variable measurement sampling technology of a power electronic control and embedded control system, in particular to a frequency planning and ADC (analog to digital converter) sampling scheduling method and system. Background In power electronic control systems, such as rectifiers, inverters, energy storage converters or motor drive systems, it is often necessary to periodically sample the current, voltage, etc. signals to achieve closed loop control. The sampling operation is typically done by an analog-to-digital converter (ADC) and the sampling is triggered at a predetermined time by a PWM timer. In a multiple converter system, different converters generally have respective PWM periods, and ADC sampling trigger points are set in the respective PWM periods, and if the ADC sampling trigger points do not have strict periodicity, sampling jitter may occur to cause a problem of low signal-to-noise ratio. When multiple converters share the same controller or share a limited amount of ADC resources, different sampling trigger events may coincide or nearly coincide on the time axis. Since an ADC usually performs only one conversion operation at the same time, when multiple sampling triggers arrive at the same time, the system may perform conversion by means of trigger arbitration or sequential queuing, so that part of sampling operations are delayed relative to the original design trigger time, and even sampling loss occurs. Sampling trigger collisions may result in sampling periods that no longer remain evenly distributed or even sampling points are lost, thereby affecting the accuracy of the sampled signal and potentially adversely affecting the performance of the control system. Therefore, how to reasonably construct the ADC sampling trigger sequences of each converter in the multi-converter system, so that the different sampling events avoid collision on the time axis, becomes a key technical problem to be solved. In the prior engineering practice, the probability of sampling conflict is generally reduced by increasing the number of ADCs, using different ADC channels or manually adjusting the trigger time. However, these methods often rely on specific hardware resource configurations, increasing system cost, and lack of a uniform timing structure method, and when the system scale is enlarged or PWM frequency combinations are changed, the problem of sampling trigger coincidence may still occur. Disclosure of Invention Aiming at the problems in the prior art, the invention provides a multi-converter frequency planning and ADC sampling scheduling method and system, which aim to avoid ADC resource conflict caused by sampling superposition in a multi-converter system, ensure the certainty and stability of sampling time in the multi-converter system and further improve the sampled data quality. In order to solve the technical problems, the invention adopts the following technical scheme: a multi-transducer frequency planning and ADC sampling scheduling method comprising the steps of: S101, acquiring sampling frequencies of all converters in a multi-converter system; s102, calculating the least common multiple of the sampling frequency of each converter; s103, calculating a unified time base frequency and a unified time base period according to the least common multiple; S104, sampling the safe distance time of the multi-converter system, wherein the safe distance time is the minimum time interval allowed between any two sampling triggers, judging whether the unified time base period is larger than or equal to the safe distance time, if so, jumping to execute the next step, otherwise, judging whether the safe distance time can be reduced, if the safe distance time can be reduced, jumping to the step S104, if not, further judging whether the least common multiple of the sampling frequency of each converter can be reduced, if the least common multiple of the sampling frequency of each converter can be reduced, jumping to the step S103, and if the least common multiple of the sampling frequency of each converter can not be reduced, judging that the system does not meet the requirement, ending and exiting; s105, distributing sampling trigger offset time to each converter according to the unified time base frequency; S106, generating ADC trigger sequences of the converters according to the sampling trigger offset time allocated to the converters. Optionally, the functional expression for calculating the least common multiple of the sampling frequency of each converter in step S102 is: ; Wherein, the Is the least common multiple of the sampling frequency of each converter,In order to find the function of the least common multiple,~Respectively 1 st to 1 stThe sampling frequency of the individual converters is chosen,Is the total number of converters in the multi-converter system.