CN-122026696-A - Control circuit and method for reducing reverse recovery charge in a switching converter

Abstract

The invention provides a control circuit and a control method for reducing reverse recovery charge in a switching converter. The control circuit is used for controlling the switching converter according to the pulse width modulation signal, wherein the switching converter comprises a first transistor and a second transistor which are coupled to the switching node together and used for switching the inductor according to the pulse width modulation signal so as to convert the input voltage to generate the output voltage. The control circuit comprises a driving circuit and an amplifying circuit, wherein the driving circuit is used for generating a switching driving signal according to a pulse width modulation signal and a switching signal on a switching node so as to switch the first transistor, the amplifying circuit is used for amplifying the difference value between the switching signal and a reference signal in dead time so as to generate an amplified output signal, and the first transistor is controlled through linear negative feedback operation so as to adjust the voltage of the switching signal to be not lower than a preset negative voltage, thereby preventing the body diode of the first transistor from being forward conducted or reducing the reverse recovery charge of the body diode.

Inventors

• ZHU GUANREN
• YANG DAYONG

Assignees

• 立锜科技股份有限公司

Dates

Publication Date

20260512

Application Date

20250430

Priority Date

20241112

Claims (20)

1. 1. A control circuit for controlling a switching converter according to a pulse width modulation signal, wherein the switching converter comprises a first transistor and a second transistor commonly coupled to a switching node for switching an inductor according to the pulse width modulation signal to convert an input voltage to generate an output voltage, the control circuit comprising: A driving circuit for generating a switching driving signal according to the PWM signal and a switching signal on the switching node to switch the first transistor, and And the amplifying circuit is used for amplifying the difference value between the switching signal and a reference signal in a dead time to generate an amplified output signal, and controlling the first transistor through a linear negative feedback operation to adjust the voltage of the switching signal to be not lower than a preset negative voltage, so that the forward conduction of a body diode of the first transistor is avoided, or the reverse recovery charge of the body diode is reduced.
2. 2. The control circuit of claim 1, wherein the driving circuit is configured to generate the switching driving signal to switch the first transistor according to a first control signal and a second control signal, wherein the first control signal is related to the pulse width modulation signal and the second control signal is related to the switching signal; The first transistor is controlled by the amplified output signal, wherein the switching drive signal is high output impedance in the dead time, and the first transistor is controlled by the switching drive signal in the switching time outside the dead time.
3. 3. The control circuit of claim 2, wherein the driving circuit comprises a first switch and a second switch; Wherein, at a conduction time in the switching time, the first switch controls the switching driving signal to be enabled according to the first control signal, thereby switching the first transistor to be on; And the second switch controls the switching driving signal to be forbidden according to the second control signal at a non-conduction time in the switching time, so that the first transistor is switched to be non-conduction.
4. 4. The control circuit of claim 3, wherein the second control signal controls the switching driving signal to be disabled when the switching signal exceeds a predetermined threshold voltage, thereby switching the first transistor to be non-conductive.
5. 5. The control circuit of claim 4, wherein a gate of the second switch is controlled by the second control signal, and the second control signal is coupled to the switching signal, wherein the predetermined threshold voltage corresponds to an on threshold voltage of the second switch.
6. 6. The control circuit of claim 2, further comprising a clamping circuit for generating the second control signal according to the switching signal and for clamping the second control signal to a clamping voltage level.
7. 7. The control circuit of claim 6, wherein the clamping voltage level is lower than a maximum rated voltage of the second switch.
8. 8. The control circuit of claim 6, further comprising a high pass filter coupled between the clamp and the second control signal for filtering the switching signal to generate the second control signal, such that when the switching signal has a high frequency component, the second switch controls the switching driving signal to be disabled, thereby switching the first transistor to be non-conductive.
9. 9. The control circuit of claim 8, wherein the amplifying circuit controls the amplified output signal to be kept disabled according to a difference between the switching signal and the reference signal after the first transistor is turned to be non-conductive, so that the first transistor is kept non-conductive.
10. 10. The control circuit of claim 1, wherein the absolute value of the predetermined negative voltage is less than a forward turn-on voltage of the body diode of the first transistor.
11. 11. The control circuit of claim 1, wherein the amplifying circuit comprises a common base amplifier or a common gate amplifier and has an input offset voltage, wherein the input offset voltage is related to the predetermined negative voltage.
12. 12. The control circuit of claim 1, wherein the amplified output signal is clamped to not lower than a predetermined level that is higher than an on threshold voltage of the first transistor.
13. 13. The control circuit of claim 12, wherein the amplifying circuit comprises a pull-down transistor and a clamp transistor electrically connected in series in sequence to the amplified output signal, wherein the pull-down transistor is configured to provide a pull-down driving force for the amplified output signal according to a difference between the switching signal and the reference signal, wherein the clamp transistor is configured as a diode-coupled transistor.
14. 14. A control method is used for controlling a switching converter according to a pulse width modulation signal, wherein the switching converter comprises a first transistor and a second transistor which are coupled to a switching node together and used for switching an inductor according to the pulse width modulation signal so as to convert an input voltage to generate an output voltage, and the control method comprises the following steps: Generating a switching driving signal according to the PWM signal and a switching signal on the switching node to switch the first transistor, and Amplifying the difference between the switching signal and a reference signal at a dead time to generate an amplified output signal; wherein the step of generating the amplified output signal comprises: The first transistor is controlled by a linear negative feedback operation to regulate the voltage of the switching signal not lower than a preset negative voltage, thereby preventing a body diode of the first transistor from being conducted forward or reducing the reverse recovery charge of the body diode.
15. 15. The method of claim 14, wherein generating the switching drive signal comprises generating the switching drive signal to switch the first transistor according to a first control signal and a second control signal, wherein the first control signal is related to the PWM signal and the second control signal is related to the switching signal; The switching driving signal is high output impedance and the amplified output signal is low output impedance in the dead time, wherein the switching driving signal is low output impedance and the amplified output signal is high output impedance in a switching time except the dead time.
16. 16. The control method of claim 15, wherein the step of generating the switching drive signal comprises: A conducting time in the switching time, controlling the switching driving signal to be enabled according to the first control signal, thereby switching the first transistor to be conducting, and And controlling the switching driving signal to be forbidden according to the second control signal at a non-conduction time in the switching time, so as to switch the first transistor to be non-conduction.
17. 17. The method of claim 16, wherein the step of generating the switching drive signal includes controlling the switching drive signal to go disabled when the switching signal exceeds a predetermined threshold voltage, thereby switching the first transistor to be non-conductive.
18. 18. The method of claim 15, further comprising generating the second control signal according to the switching signal and clamping the second control signal to be no greater than a clamping voltage level.
19. 19. The control method of claim 18, wherein the clamping voltage level is lower than a maximum rated voltage of the second switch.
20. 20. The control method according to claim 18, further comprising: Filtering the switching signal to generate the second control signal, and When the switching signal has a high frequency component, the switching driving signal is controlled to be turned to be disabled, thereby switching the first transistor to be turned to be non-conductive.

Description

Control circuit and method for reducing reverse recovery charge in a switching converter Technical Field The present invention relates to a control circuit, and more particularly, to a control circuit capable of reducing reverse recovery charges in a switching converter. The invention also relates to a control method for reducing reverse recovery charge in a switching converter. Background Fig. 1A shows a prior art switching converter. As shown in fig. 1A, the control signals SH and SL generate non-overlapping switching driving signals DRVH and DRVL via the logic circuit to control the switching of the upper bridge transistor 42 and the lower bridge transistor 41, respectively. When the upper bridge transistor 42 is turned on, the input voltage VIN energizes the inductor 30 and charges the output capacitor via the switching node LX, thereby generating the output voltage VO. When the lower bridge transistor 41 is controlled to be turned on by the switching drive signal DRVL after the upper bridge transistor 42 is turned off, the inductor 30 is demagnetized and its current can freewheel through the lower bridge transistor 41. Fig. 1B shows an operation waveform diagram of a prior art switching converter. As shown in fig. 1B, at a Dead Time (DT) before the start of the next switching cycle, both the upper bridge transistor 42 and the lower bridge transistor 41 are in an off state, resulting in the current of the inductor 30 flowing through the body diode 43 inside the lower bridge transistor 41. During the dead time DT, the voltage VLX of the switching node LX drops to a difference between zero voltage and the forward turn-on voltage Vf of the body diode 43 (e.g., -0.7V). When the next switching cycle starts, the upper bridge transistor 42 is controlled to be turned on by the switching driving signal DRVH, and the body diode 43 must be turned from forward on to off, so that a large amount of reverse recovery charges (reverse recovery charge, qrr) are generated. This reverse recovery current, together with the parasitic inductance, forms a resonant circuit, resulting in a voltage spike (voltage spike) at the switching node LX that may even exceed the maximum rated voltage (maximum rated voltage) of the upper and lower bridge transistors 42, 41 or other related components, thereby causing system reliability problems and even damaging the device. The prior art switching converter 1001 suppresses the voltage spike at the switching node LX by a filter circuit composed of a capacitor 81 and a resistor 82. However, although the filter circuit is capable of absorbing part of the parasitic oscillation energy and reducing the spike voltage, power loss is caused because the capacitor 81 needs to be charged and discharged every switching period and the energy is eventually consumed by the resistor 82 in the form of heat energy. The amount of loss is related to the capacitance of the capacitor 81, the input voltage VIN, and the switching frequency, and also continuously generates loss under no-load conditions. In addition, the parasitic inductor 91 and the filter circuit together form resonance, which affects the filtering effect, resulting in limited suppression effect and failure to effectively eliminate high frequency noise and voltage spike generated by the reverse recovery of the body diode. In view of the above, to overcome the drawbacks of the prior art, the present invention provides a control circuit for reducing reverse recovery charges in a switching converter. Compared with the situation that the inductor current of the lower bridge transistor must flow through the body diode to cause reverse recovery charge accumulation after the idle time is forbidden in the prior art, the gate of the lower bridge transistor is simultaneously coupled with the driving circuit and the amplifying circuit, and the amplifying circuit continuously controls the lower bridge transistor to be moderately conducted in the idle time, so that the inductor current can continuously flow through the main channel (rather than the body diode) of the lower bridge transistor, and the reverse recovery charge accumulation is avoided or reduced. Disclosure of Invention In one aspect, the present invention provides a control circuit for controlling a switching converter according to a pwm signal, wherein the switching converter includes a first transistor and a second transistor coupled together at a switching node for switching an inductor according to the pwm signal to convert an input voltage to generate an output voltage, the control circuit includes a driving circuit for generating a switching driving signal according to the pwm signal and a switching signal at the switching node to switch the first transistor, and an amplifying circuit for amplifying a difference between the switching signal and a reference signal at a dead time to generate an amplified output signal, and controlling the first transistor by a linear negative feedback operation