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CN-122026717-A - Bare chip, chip packaging structure and electronic equipment

CN122026717ACN 122026717 ACN122026717 ACN 122026717ACN-122026717-A

Abstract

The application provides a bare chip, a chip packaging structure and electronic equipment, which can adapt to the power supply requirement of a multi-stage inverter in a data channel under the condition of not occupying external power supply resources. The die includes at least one charge pump and at least one data channel therein. The power supply terminal of the charge pump is connected to the high-level power supply terminal and the low-level power supply terminal. The data channel comprises a first channel and a second channel, wherein the first channel comprises a first inverter which is connected in series in multiple stages, and the second channel comprises a second inverter which is connected in series in multiple stages. The first power end of the first inverter connected in series in multiple stages is connected with the high-level power end, the second power end of the second inverter connected in series in multiple stages is connected with the low-level power end, the output end of the charge pump is connected with the second power end of the first inverter connected in series in multiple stages and the first power end of the second inverter connected in series in multiple stages, and a first level is provided, and the first level is an intermediate level between the high-level power end and the low-level power end.

Inventors

  • BAI XINGXING
  • LI DING
  • LIU ZHE
  • Bao Qinglei

Assignees

  • 华为技术有限公司

Dates

Publication Date
20260512
Application Date
20241106

Claims (14)

  1. 1. The bare chip is characterized by comprising at least one charge pump, at least one data channel, a high-level power supply end and a low-level power supply end, wherein the charge pump comprises an output end, and the power supply end of the charge pump is connected to the high-level power supply end and the low-level power supply end; The data channel comprises a first channel and a second channel, wherein the first channel comprises a first inverter which is connected in series in multiple stages, and the second channel comprises a second inverter which is connected in series in multiple stages; the first power end of the first inverter connected in series with the multiple stages is connected with the high-level power end, and the second power end of the first inverter connected in series with the multiple stages is connected with the output end; the first power end of the multistage series-connected second inverter is connected with the output end, and the second power end of the multistage series-connected second inverter is connected with the low-level power end; The output end of the charge pump provides a first level for the second power end of the first inverter connected in series with the multiple stages and the first power end of the second inverter connected in series with the multiple stages, and the first level is the intermediate level between the high-level power end and the low-level power end.
  2. 2. The die of claim 1, wherein the die is configured to receive a plurality of chips, The bare chip comprises a plurality of data channels and a plurality of charge pumps, wherein the data channels are respectively connected with different charge pumps.
  3. 3. The die of claim 1 or 2, further comprising a control circuit for generating a first clock signal and a second clock signal; The charge pump is configured to output the first level through the output terminal under control of the first clock signal and the second clock signal.
  4. 4. The die of claim 3, wherein the charge pump comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitance; a gate of the first transistor is connected to the first clock signal terminal, a first pole of the first transistor is connected to the high-level power supply terminal, and a second pole of the first transistor is connected to a first end of the first capacitor; A gate of the second transistor is connected to the second clock signal terminal, a first pole of the second transistor is connected to the output terminal, and a second pole of the second transistor is connected to the first terminal of the first capacitor; a gate of the third transistor is connected to the first clock signal terminal, a first pole of the third transistor is connected to the output terminal, and a second pole of the third transistor is connected to the second terminal of the first capacitor; A gate of the fourth transistor is connected to the second clock signal terminal, a first pole of the fourth transistor is connected to the low-level power supply terminal, and a second pole of the fourth transistor is connected to a second terminal of the first capacitor; one of the first pole and the second pole of the first transistor, the second transistor, the third transistor and the fourth transistor is a source electrode, and the other is a drain electrode.
  5. 5. The die of any of claims 1-4, wherein, The die further comprises a first D trigger, a first buffer and a second D trigger, wherein the output end of the first D trigger is connected with the input end of the first inverter which is connected in series with the plurality of stages, the output end of the first inverter which is connected in series with the plurality of stages is connected with the input end of the first buffer, and the output end of the first buffer is connected with the input end of the second D trigger; The die further comprises a third D trigger, a second buffer and a fourth D trigger, wherein the output end of the third D trigger is connected with the input end of the second inverter which is connected in series with the plurality of stages, the output end of the second inverter which is connected in series with the plurality of stages is connected with the input end of the second buffer, and the output end of the second buffer is connected with the input end of the fourth D trigger.
  6. 6. The die of any of claims 1-5, wherein the die is a network chip.
  7. 7. A chip package structure comprising a substrate and the die of any one of claims 1-6, the die being disposed on the substrate and electrically connected to the substrate.
  8. 8. The chip package structure of claim 7, wherein, The chip packaging structure also comprises a filter circuit, wherein the filter circuit is connected with the output end and is used for filtering the level output by the output end.
  9. 9. The chip package structure of claim 8, wherein, The filter circuit comprises a second capacitor, and the second capacitor is connected between the high-level power supply end and the output end.
  10. 10. The chip package structure according to claim 8 or 9, wherein, The filter circuit comprises a third capacitor, and the third capacitor is connected between the low-level power supply end and the output end.
  11. 11. The chip package structure according to any one of claims 8 to 10, wherein, The filter circuit comprises a fourth capacitor, a plurality of resistors and a plurality of inductors; the fourth capacitor is connected between the low-level power end and the output end, and the resistors and the inductors are alternately connected in series between the fourth capacitor and the output end.
  12. 12. The chip package structure according to any one of claims 8 to 11, wherein, And the output ends of the charge pumps are connected with the same filter circuit.
  13. 13. The chip package structure according to any one of claims 8 to 12, wherein, The filter circuit is disposed in the die; Or some or all of the devices in the filter circuit are disposed on the substrate independently of the die.
  14. 14. An electronic device comprising a circuit board and a die as recited in any of claims 1-6, the die being electrically connected to the circuit board.

Description

Bare chip, chip packaging structure and electronic equipment Technical Field The present application relates to the field of power technologies, and in particular, to a die, a chip package structure, and an electronic device. Background The area of the chip (especially the network chip) covered by the long-distance wiring can reach 50%, the traditional wiring mode is full swing, the voltage swing of the wiring is between 0 and VDD, and the wiring power consumption can be more than 17% in the total power consumption by adopting the wiring mode. In order to reduce the wiring power consumption, as shown in fig. 1, a new wiring method is provided in the prior art, and the wiring method adopts a voltage stack bus (voltage stacking bus, VSB) to stack (INV STACKING) multiple inverter stages, so that current sharing can be realized between an upper channel (top channel) and a lower channel (bottom channel), and the purpose of reducing the power consumption can be achieved. In this scheme, an intermediate level Vmid is required to be introduced by a low dropout regulator (lowdropoutregulator, LDO), and the standard value of the intermediate level Vmid is 0.5 x vdd. the signal swing of the top channel and the bottom channel is 0.5*VDD,top channe, the signal swings between 0.5 and 0.5 of VDD, and the bottom channel swings between 0 and 0.5 of VDD. In the case where the top channel and bottom channel currents are perfectly matched, the intermediate level Vmid can naturally settle at 0.5 x vdd. However, due to the randomness of the code pattern, a regulated supply of the intermediate level Vmid is required. The existing LDOs are divided into two types, namely an on-chip LDO (onchiplowdropout power, OCLDC) and an off-chip LDO (external LDO). The on-chip LDOs are integrated into a larger IP core (intellectual propertycore), and require additional analog and digital power supplies, which can occupy die pad (ball) resources. The off-chip LDO occupies power resources of the circuit board (printed circuit board, PCB) and package (package), and cannot match the widely distributed voltage stack bus VSB requirements in the chip. Disclosure of Invention The application provides a bare chip, a chip packaging structure and electronic equipment, which can adapt to the power supply requirement of a multi-stage inverter in a data channel under the condition of not occupying external power supply resources. The application provides a bare chip (chip) which comprises at least one charge pump, at least one data channel, a high-level power supply terminal VDD and a low-level power supply terminal VSS. The charge pump includes an output terminal, and a power supply terminal of the charge pump is connected to a high-level power supply terminal and a low-level power supply terminal. Each data channel includes a first channel and a second channel. The first channel comprises a first inverter connected in series in multiple stages, and the second channel comprises a second inverter connected in series in multiple stages. The first power end of the first inverter connected in series in multiple stages is connected with the high-level power end, and the second power end of the first inverter connected in series in multiple stages is connected with the output end. The first power end of the second inverter connected in series in multiple stages is connected with the output end, and the second power end of the second inverter connected in series in multiple stages is connected with the low-level power end. The output end of the charge pump provides a first level for the second power end of the first inverter connected in series in multiple stages and the first power end of the second inverter connected in series in multiple stages, and the first level is the intermediate level between the high-level power end and the low-level power end. The intermediate level is equal to or approximately equal to half the voltage at the high level power supply terminal. That is, in the chip provided by the application, the data channel adopts the wiring mode of the voltage stack bus (voltage stacking bus, VSB), in this case, the signal swing of the first channel and the second channel in the data channel can be reduced, and the current sharing can be realized, so that the purpose of reducing the power consumption can be achieved. On the basis, the chip adopts the charge pump in the chip to supply power to the multi-stage inverter in the first channel and the second channel, on one hand, board-level power supply resources are not occupied, namely power supply resources of a circuit board (PCB) and a package (package) are not occupied, on the other hand, the charge pump does not need external power supply resources, the original power supply ends (VDD and VSS) in the chip can meet the requirements, welding point (bump and ball) resources of the chip are not occupied, the charge pump has high efficiency, occupies small area, can be flexibly distributed in the chip,