CN-122026722-A - Control circuit capable of automatically switching working modes

CN122026722ACN 122026722 ACN122026722 ACN 122026722ACN-122026722-A

Abstract

The disclosure provides a control circuit capable of automatically switching a working mode, which comprises a current generation circuit, a first current difference circuit, a second current difference circuit, a valley value control circuit, a PFM detection circuit and an oscillator, wherein the current generation circuit converts control voltage into first control current, generates second control current with the same size as the first control current through a first mirror image, the first current difference circuit generates fixed bias current, the control circuit works in a PWM mode with fixed frequency when the first control current is larger than the fixed bias current, the second current difference circuit generates third control current with the same size as the first control current through a first mirror image, the valley value control circuit adjusts valley value current when a lower pipe is opened, the frequency of a lower pipe overcurrent signal is high level through reducing the frequency of a valley value current control switch node, and the control circuit reduces the frequency by reducing the valley value current when the third control current is smaller than the fixed bias current.

Inventors

LI HAONAN
Hu Shuonan
HAO JIAQI
LU ZHAOYANG

Assignees

芯洲科技(北京)股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260413

Claims (10)

1. The control circuit is characterized by being suitable for a BUCK type DC-DC converter and comprising a current generating circuit, a first current difference circuit, a second current difference circuit, a valley control circuit, a PFM detection circuit and an oscillator; the current generation circuit is configured to convert a control voltage into a first control current, and generate a second control current with the same magnitude as the first control current through a first mirror image; The first current difference circuit is configured to generate a fixed bias current, obtain a first difference current according to the difference between the fixed bias current and a second control current, generate a difference voltage based on the first difference current, and convert the difference voltage into the second difference current, wherein when the first control current is greater than the fixed bias current, the control circuit operates in a PWM mode with a fixed frequency; The second current difference circuit is configured to generate a third difference current with the same magnitude as the second difference current through a second mirror image, generate a third control current with the same magnitude as the first control current through the first mirror image, generate a first difference current with the same magnitude as the third difference current through a third mirror image, and obtain a second difference current through the third difference current and the first difference current; The valley value control circuit is configured to generate a third difference current with the same magnitude as the second difference current through a fourth mirror image, adjust the valley value current through the third difference current when the lower tube is opened, control the frequency reduction of a switch node through reducing the valley value current, and output a lower tube overcurrent signal to the oscillator, wherein when the third control current is smaller than the fixed bias current, the lower tube overcurrent signal is in a high level, and the control circuit reduces the valley value current to reduce the frequency; The PFM detection circuit is configured to compare the control voltage with a PFM threshold voltage and output a PFM signal to the oscillator, wherein when the control voltage is smaller than the PFM threshold voltage, the PFM signal is in a high level, and the control circuit works in a frequency-reduced PFM mode; The oscillator is configured to perform a logical OR of the down pipe overcurrent signal and the PFM signal, outputting a clock signal to a logic control circuit.
2. The control circuit for automatically switching modes of operation of claim 1, wherein the current generating circuit comprises a first operational amplifier, a first transistor, a first resistor, an on-resistance of a top tube sampling tube, a second transistor, and a second resistor; the non-inverting input end of the first operational amplifier is coupled with the PFM detection circuit and is connected with the control voltage, the inverting input end of the first operational amplifier is respectively coupled with the second pole of the first transistor and the first end of the first resistor, and the output end of the first operational amplifier is respectively coupled with the control pole of the first transistor and the control pole of the second transistor; the first end of the on-resistance of the upper tube sampling tube is connected with an input voltage, the second end of the on-resistance of the upper tube sampling tube is respectively coupled with the first pole of the first transistor and the first current difference circuit, and the on-resistance of the upper tube sampling tube is configured to generate a set current according to the input voltage; a first pole of the second transistor is coupled to the first current difference circuit, and a second pole is coupled to a first end of the second resistor; the second end of the first resistor and the second end of the second resistor are respectively grounded; wherein the first operational amplifier, the first transistor, and the first resistor constitute a first voltage-to-current circuit configured to convert the control voltage into a first control current flowing through the first transistor.
3. The control circuit for automatically switching modes of operation of claim 2, wherein the first current difference circuit comprises a current source, a third resistor, and a second voltage-to-current circuit, wherein the second voltage-to-current circuit comprises a second operational amplifier, a third transistor, and a fourth resistor, the second voltage-to-current circuit configured to convert the difference voltage to a second difference current flowing through the third transistor; the first end of the current source is connected to a power supply voltage, the second end of the current source is respectively coupled with the first pole of the second transistor, the non-inverting input end of the second operational amplifier and the first end of the third resistor, the current source is configured to provide the fixed bias current, when the first control current is larger than the fixed bias current, the first difference current flowing to the first end of the third resistor is 0, the set current is equal to the first control current, and the control circuit works in a PWM mode with fixed frequency; a second terminal of the third resistor is grounded, and the third resistor is configured to generate a difference voltage based on the first difference current; the non-inverting input end of the second operational amplifier is connected with the difference voltage, the inverting input end of the second operational amplifier is respectively coupled with the second pole of the third transistor and the first end of the fourth resistor, and the output end of the second operational amplifier is respectively coupled with the control pole of the third transistor and the second current difference circuit; a first electrode of the third transistor is coupled with a second end of the on-resistance of the upper tube sampling tube; The second end of the fourth resistor is grounded.
4. The control circuit for automatically switching operation modes according to claim 3, wherein the second current difference circuit comprises a fourth transistor, a fifth resistor, a fifth transistor, a sixth resistor, a sixth transistor, a seventh transistor, and an eighth transistor; The control electrode of the fourth transistor is coupled to the control electrode of the third transistor and the output end of the second operational amplifier respectively, the first electrode is coupled to the control electrode of the sixth transistor, the first electrode of the sixth transistor and the control electrode of the seventh transistor respectively, the second electrode is coupled to the first end of the fifth resistor, the fourth transistor is configured to generate a third difference current with the same magnitude as the second difference current through a second mirror image, and the third transistor and the fourth transistor form a second current mirror circuit; The control electrode of the fifth transistor is respectively coupled with the control electrode of the second transistor, the control electrode of the first transistor and the output end of the first operational amplifier, the first electrode is respectively coupled with the first electrode of the seventh transistor, the control electrode of the eighth transistor and the first electrode of the eighth transistor, the second electrode is coupled with the first end of the sixth resistor, the fifth transistor is configured to generate a third control current with the same magnitude as the first control current through a first mirror image, and the first transistor, the second transistor and the fifth transistor form a first current mirror circuit; the second pole of the sixth transistor is respectively coupled with the second pole of the seventh transistor, the second pole of the eighth transistor and the valley value control circuit, and is connected with the power supply voltage; The seventh transistor is configured to generate a first difference current having the same magnitude as the third difference current through a third mirror image, and the sixth transistor and the seventh transistor constitute a third current mirror circuit; a control pole and a second pole of the eighth transistor are both coupled to a valley control circuit, the eighth transistor being configured to generate the second differencing current when the third control current is less than the fixed bias current.
5. The control circuit for automatically switching modes of operation according to claim 4, wherein the valley control circuit comprises a ninth transistor, a down tube sampling tube, a down tube and a comparator; The control electrode of the ninth transistor is respectively coupled with the control electrode of the eighth transistor and the first electrode of the eighth transistor, the first electrode is respectively coupled with the second electrode of the lower tube sampling tube and the non-inverting input end of the comparator, the second electrode is respectively coupled with the second electrode of the eighth transistor, the second electrode of the seventh transistor and the second electrode of the sixth transistor, the ninth transistor is configured to generate a third difference current with the same magnitude as the second difference current through a fourth mirror image, and the eighth transistor and the ninth transistor form a fourth current mirror circuit; The control electrode of the lower tube sampling tube is coupled with the control electrode of the lower tube, a lower tube driving signal is accessed, the first electrode of the lower tube sampling tube is coupled with the first electrode of the lower tube through a switch node, and the second electrode of the lower tube is grounded; the inverting input end of the comparator is grounded, and the down-pipe overcurrent signal is output from the output end to the oscillator.
6. The control circuit for automatically switching an operation mode according to claim 5, wherein in the valley control circuit, a valley current is detected by detecting a voltage of a switching node, and when it is detected that the valley current falls to a preset value, the down-pipe overcurrent signal output to the oscillator is high level.
7. The control circuit for automatically switching modes of operation according to claim 6, wherein the valley control circuit controls the switching frequency to decrease by decreasing the valley current when the third control current is less than the fixed bias current, the control circuit operating in the valley down mode.
8. The control circuit for automatically switching modes of operation according to claim 2, wherein the PFM detection circuit comprises a hysteresis comparator; the non-inverting input end of the hysteresis comparator is connected with the PFM threshold voltage, the inverting input end of the hysteresis comparator is coupled with the non-inverting input end of the first operational amplifier and connected with the control voltage, the hysteresis comparator is configured to compare the control voltage with the PFM threshold voltage and output a PFM signal to the oscillator, wherein when the control voltage changes from large to small, the PFM threshold voltage is a falling PFM threshold voltage, and when the control voltage changes from small to large, the PFM threshold voltage is a rising PFM threshold voltage.
9. A BUCK-type DC-DC converter comprising the control circuit for automatically switching operation modes according to any one of claims 1 to 8.
10. A chip comprising the BUCK-type DC-DC converter of claim 9.

Description

Control circuit capable of automatically switching working modes Technical Field The present disclosure relates to the field of integrated circuit technologies, and in particular, to a control circuit capable of automatically switching operating modes. Background In different modulation modes of the BUCK type DC-DC converter, pulse width modulation (Pulse Width Modulation, abbreviated as PWM) adopts a fixed switching frequency to control the switch to be turned on, and modulates the output voltage by changing the on time of the switch, the PWM mode has high conversion efficiency under the heavy load condition, but as the load is lightened, if each period performs switching action, the switching loss of the power switch tube greatly reduces the conversion efficiency, pulse frequency modulation (Pulse Frequency Modulation, abbreviated as PFM) is also called a variable frequency modulation mode, the modulation of duty ratio is realized by changing the working frequency of the switch, and the switching frequency is reduced along with the load reduction, thereby improving the conversion efficiency under the light load. At present, a BUCK DC-DC converter often adopts a double-working mode of pwm+pfm to realize high efficiency of full load, works in PWM mode when the load is large, and switches to PFM mode when the load is reduced to a small value to improve efficiency. However, when the BUCK type DC-DC converter is at the critical PFM, it will switch back and forth between PFM and PWM modes of operation, resulting in unstable output voltage and increased ripple. Disclosure of Invention The main object of the present disclosure is to provide a control circuit for automatically switching operation modes. In order to achieve the above object, a first aspect of the present disclosure provides a control circuit for automatically switching an operation mode, which is suitable for a BUCK DC-DC converter, and includes a current generating circuit, a first current difference circuit, a second current difference circuit, a valley control circuit, a PFM detecting circuit, and an oscillator; The current generation circuit is configured to convert the control voltage into a first control current, and generate a second control current with the same magnitude as the first control current through a first mirror image; The first current difference circuit is configured to generate a fixed bias current, obtain a first difference current according to a difference value between the fixed bias current and the second control current, generate a difference voltage based on the first difference current, and convert the difference voltage into the second difference current, wherein when the first control current is greater than the fixed bias current, the control circuit operates in a PWM mode of a fixed frequency; the second current difference circuit is configured to generate a third difference current with the same magnitude as the second difference current through the second mirror image, generate a third control current with the same magnitude as the first control current through the first mirror image, generate a first difference current with the same magnitude as the third difference current through the third mirror image, and obtain a second difference current through the third difference current and the first difference current; The valley value control circuit is configured to generate a third difference current with the same magnitude as the second difference current through a fourth mirror image, adjust the valley value current through the third difference current when the lower tube is opened, control the frequency reduction of the switch node through reducing the valley value current, and output a lower tube overcurrent signal to the oscillator, wherein when the third control current is smaller than the fixed bias current, the lower tube overcurrent signal is in a high level, and the control circuit reduces the valley value current to reduce the frequency; The PFM detection circuit is configured to compare the control voltage with the PFM threshold voltage and output a PFM signal to the oscillator, wherein when the control voltage is smaller than the PFM threshold voltage, the PFM signal is high, and the control circuit works in a frequency-reduced PFM mode; the oscillator is configured to perform a logical OR of the down pipe overcurrent signal and the PFM signal, and to output a clock signal to the logic control circuit. Optionally, the current generating circuit includes a first operational amplifier, a first transistor, a first resistor, an on-resistance of the upper tube sampling tube, a second transistor, and a second resistor; The non-inverting input end of the first operational amplifier is coupled with the PFM detection circuit and is connected with the control voltage, the inverting input end of the first operational amplifier is respectively coupled with the second pole of the first transistor and the first end o