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CN-122026778-A - Encoder frequency division method and related device

CN122026778ACN 122026778 ACN122026778 ACN 122026778ACN-122026778-A

Abstract

The application discloses an encoder frequency division method and a related device, and relates to the technical field of encoder frequency division, wherein the encoder frequency division method comprises the following steps: the level conditions of the A phase signal and the B phase signal output by the encoder are monitored, when the encoder is in a normal output state, the phase relation of the A phase signal and the B phase signal is determined, and when the level of the A phase signal and the B phase signal is changed, accumulation of the signal change number is carried out, and when the signal change number is 1, N+1, 2N+1, 3N+1 and 4N+1, corresponding frequency division signals are output, so that pulse output with the duty ratio of 50% can be realized when the frequency division number N is odd or even. The application is based on an encoder frequency division method. The frequency division output with the duty ratio of 50% is realized based on the encoder at the software end, the frequency division output with the duty ratio of 50% is not influenced by the odd and even frequency division numbers, the related circuit structure is simplified, and the frequency division mode of the encoder is optimized.

Inventors

  • ZHENG WEI
  • ZHANG HONGDA
  • CAO LIYAN

Assignees

  • 深圳市海浦蒙特科技有限公司

Dates

Publication Date
20260512
Application Date
20260130

Claims (10)

  1. 1. A method of frequency division by an encoder, comprising: respectively monitoring the level conditions of an A-phase signal and a B-phase signal output by an encoder of a motor, and monitoring whether the encoder is in a normal output state or not based on the level conditions; Determining a phase relationship between the A-phase signal and the B-phase signal based on the level condition when the encoder is in a normal output state, and accumulating the signal change number of the encoder by one when the A-phase signal level changes and accumulating the signal change number of the encoder by one when the B-phase signal level changes, wherein the initial value of the signal change number is zero; Detecting the numerical value of the signal change number after the signal change number is changed; When the value of the signal change number is detected to be 1, the phase relation of the current state of the encoder is obtained to be used as a periodic phase relation, and an A-phase frequency division signal of the encoder is output to be an A-phase first frequency division signal which is a preset high-level signal or low-level signal; When the value of the signal change number is detected to be N+1, determining the B-phase first frequency division signal based on the periodic phase relation, and outputting the B-phase frequency division signal of the encoder as the B-phase first frequency division signal; When the value of the signal change number is 2N+1, determining an A-phase second frequency division signal of the encoder based on the A-phase first frequency division signal, and adjusting and outputting the A-phase frequency division signal of the encoder as the A-phase second frequency division signal; when the value of the signal change number is 3N+1, determining the B-phase second frequency division signal based on the B-phase first frequency division signal, and adjusting and outputting the B-phase frequency division signal of the encoder into the B-phase second frequency division signal; Resetting the value of the signal variation number to 1 after detecting that the value of the signal variation number is 4n+1, re-executing the step of obtaining the phase relation of the current state of the encoder as a periodic phase relation after detecting that the value of the signal variation number is 1, and outputting an A-phase frequency division signal of the encoder as an A-phase first frequency division signal; wherein, N is the frequency division number of the encoder; and identifying the running state of the motor based on the output A-phase frequency division signal and the B-phase frequency division signal.
  2. 2. The method of claim 1, wherein monitoring the level conditions of the a-phase signal and the B-phase signal output from the encoder of the motor, respectively, and monitoring whether the encoder is in a normal output state based on the level conditions, comprises: When the encoder outputs the A-phase signal, monitoring the interval time of rising edge or falling edge of the level of the A-phase signal, if the interval time is not greater than a preset interval time threshold value, setting a first signal early warning value to 0 so as to determine that the A-phase signal is a normal output signal, and if the interval time is greater than the preset interval time threshold value, setting the first signal early warning value to 1 so as to determine that the A-phase signal is an abnormal output signal; When the encoder outputs the B-phase signal, monitoring the interval time of rising edge or falling edge of the level of the B-phase signal, if the interval time is not greater than a preset interval time threshold value, setting a second signal early warning value to 0 so as to determine that the B-phase signal is a normal output signal, and if the interval time is greater than the preset interval time threshold value, setting the second signal early warning value to 1 so as to determine that the B-phase signal is an abnormal output signal; And if the first signal early warning value and the second signal early warning value are both 0, determining that the encoder is in a normal output state.
  3. 3. The encoder frequency division method of claim 2, further comprising: Detecting the first signal early warning value and the second signal early warning value when the frequency division coefficient is required to be switched externally; if the first signal early warning value and the second signal early warning value are both 1, switching the frequency division coefficient; If either the first signal early warning value or the second signal early warning value is 0, the original frequency division coefficient is maintained.
  4. 4. The encoder frequency division method of claim 2, further comprising: if the first signal early warning value is detected to be 1 and the second signal early warning value is detected to be 0; or detecting that the second signal early warning value is 1 and the second signal early warning value is 0; And determining that the encoder is in an abnormal output state, and controlling the encoder to stop outputting the A-phase frequency division signal and the B-phase frequency division signal.
  5. 5. The encoder frequency division method of claim 4, further comprising: When the encoder enters a normal output state for the first time or again, detecting a first signal early warning value and the second signal early warning value again; And if the first signal early warning value and the second signal early warning value are detected to be 1, setting the first signal early warning value and the second signal early warning value to 0.
  6. 6. The encoder frequency division method of claim 1, wherein the determining the phase relationship of the a-phase signal and the B-phase signal based on the level condition comprises: when the level rising edge of the A-phase signal is monitored, if the A-phase signal is at a high level and the B-phase signal is at a low level, determining that the phase of the A-phase signal leads the phase of the B-phase signal; when the level falling edge of the A phase signal is detected, if the A phase signal is at a low level and the B phase signal is at a high level, determining that the phase of the B phase signal leads the phase of the B phase signal.
  7. 7. The encoder frequency division method of claim 6, wherein determining the B-phase first divided signal based on the phase relationship after detecting that the number of signal changes has a value of n+1 comprises: And after detecting that the value of the signal change number is N+1, if the phase of the A-phase signal is advanced from the phase of the B-phase signal, determining that the B-phase first frequency division signal is a high-level signal, and if the phase of the B-phase signal is advanced from the phase of the A-phase signal, determining that the A-phase first frequency division signal is a low-level signal.
  8. 8. The encoder frequency dividing device is characterized by comprising a processor, an encoder, a first indicator light and a second indicator light; The phase A signal output port of the encoder and the phase B signal output port of the encoder are connected to the processor; the encoder is used for outputting an A phase signal and a B phase signal to the processor; The first indicator light and the second indicator light are connected to the processor, the first indicator light is used for indicating the signal state of the A-phase signal, and the second indicator light is used for indicating the signal state of the B-phase signal; The processor is configured to execute the computer program to enable the encoder frequency dividing apparatus to implement the encoder frequency dividing method as claimed in any one of claims 1 to 7.
  9. 9. A computer program product comprising computer readable instructions which, when run on an electronic device, cause the electronic device to implement the encoder frequency division method of any one of claims 1 to 7.
  10. 10. A computer storage medium carrying one or more computer programs which, when executed by an electronic device, enable the electronic device to implement the encoder frequency division method of any one of claims 1 to 7.

Description

Encoder frequency division method and related device Technical Field The application relates to the technical field of frequency division of encoders, in particular to a frequency division method of an encoder and a related device. Background The encoder is usually arranged on a rotating shaft of the motor, the main function of the encoder is to convert the mechanical motion of the motor rotor into an electric signal, specifically, when the motor rotor rotates, the encoder usually generates two-phase (usually a-phase and B-phase) pulse signals, the pulse signals can feed back the information such as the rotating speed, the position and the direction of the motor rotor, thousands of pulse signals can be usually generated by the encoder when the motor rotor rotates at a high speed, the pulse frequency output by the encoder is also increased, and in order to facilitate the data processing, the pulse signals generated by the encoder usually need to be subjected to frequency division processing (for example, every 5 pulse signals generated by the encoder are output into 1 pulse signals, namely 5 frequency division). In the prior art, a programmable logic device (CPLD, complex Programmable Logic Device) is generally used to divide the frequency of the pulse signal of the encoder, and the programmable logic device belongs to a digital integrated circuit, and mainly uses circuit hardware units such as logic gates and triggers to divide the frequency of the pulse signal of the encoder (when 5 frequency divisions are performed, each time the encoder generates 5 pulse signals, 1 pulse signal is generated through the logic gates and related devices when the encoder is detected), because the size of the circuit specification limits the resources occupied by the logic gates and related devices, the corresponding frequency division logic control is relatively simple, and the frequency division control can only be performed generally based on the complete pulse signal of the encoder, but the frequency division control is difficult to output the pulse signal with 50% duty ratio (namely, the duration of the high and low levels of the output pulse signal is asymmetric) when the frequency division number is odd, so that the accuracy of subsequent signal processing is affected, and the accuracy of system operation is reduced. Disclosure of Invention In view of the above, the present application provides an encoder frequency division method and related apparatus, so as to achieve the purpose of frequency division of an encoder signal. The specific scheme is as follows: a first aspect of the present application provides a frequency division method of an encoder, including: respectively monitoring the level conditions of an A-phase signal and a B-phase signal output by an encoder of a motor, and monitoring whether the encoder is in a normal output state or not based on the level conditions; Determining a phase relationship between the A-phase signal and the B-phase signal based on the level condition when the encoder is in a normal output state, and accumulating the signal change number of the encoder by one when the A-phase signal level changes and accumulating the signal change number of the encoder by one when the B-phase signal level changes, wherein the initial value of the signal change number is zero; Detecting the numerical value of the signal change number after the signal change number is changed; When the value of the signal change number is detected to be 1, the phase relation of the current state of the encoder is obtained to be used as a periodic phase relation, and an A-phase frequency division signal of the encoder is output to be an A-phase first frequency division signal which is a preset high-level signal or low-level signal; When the value of the signal change number is detected to be N+1, determining the B-phase first frequency division signal based on the periodic phase relation, and outputting the B-phase frequency division signal of the encoder as the B-phase first frequency division signal; When the value of the signal change number is 2N+1, determining an A-phase second frequency division signal of the encoder based on the A-phase first frequency division signal, and adjusting and outputting the A-phase frequency division signal of the encoder as the A-phase second frequency division signal; when the value of the signal change number is 3N+1, determining the B-phase second frequency division signal based on the B-phase first frequency division signal, and adjusting and outputting the B-phase frequency division signal of the encoder into the B-phase second frequency division signal; Resetting the value of the signal variation number to 1 after detecting that the value of the signal variation number is 4n+1, re-executing the step of obtaining the phase relation of the current state of the encoder as a periodic phase relation after detecting that the value of the signal variation number is 1, and outputting