Search

CN-122026815-A - Equalizer and chip

CN122026815ACN 122026815 ACN122026815 ACN 122026815ACN-122026815-A

Abstract

The invention provides an equalizer and a chip, which comprise an amplifying module for amplifying an input high-frequency signal based on an active inductor, and a bias current module coupled with the active inductor in the amplifying module for providing bias current for the active inductor. The equalizer and the chip of the invention increase the bias current on the basis of the active inductance, can improve the high-frequency gain under the condition of not losing the low-frequency gain, thereby improving the signal attenuation in the baseband and having strong equalizing capability. In addition, the equalizer and the chip of the invention do not increase the load of the input end and the output end obviously although the bias current is increased.

Inventors

  • ZHU JUN

Assignees

  • 芯迈半导体技术(杭州)股份有限公司

Dates

Publication Date
20260512
Application Date
20260203

Claims (10)

  1. 1. An equalizer, the equalizer comprising at least: The amplifying module amplifies the input high-frequency signal based on the active inductor; And the bias current module is coupled with the active inductor in the amplifying module and provides bias current for the active inductor.
  2. 2. The equalizer of claim 1, wherein the amplifying module comprises a first active inductor, a second active inductor, a first input unit, a second input unit, and a current source; the first end of the first active inductor is coupled with a first power end, and the second end of the first active inductor is coupled with the first end of the first input unit and serves as a first output end of the amplifying module; the first end of the second active inductor is coupled with the first power end, and the second end of the second active inductor is coupled with the first end of the second input unit and serves as a second output end of the amplifying module; The second end of the first input unit and the second end of the second input unit are coupled with a second power end through the current source, and the input ends of the first input unit and the second input unit are used as differential input ends; The first power end and the second power end are respectively arranged as a power anode and a power cathode.
  3. 3. The equalizer of claim 2, wherein: the first input unit comprises a first MOS tube, a drain electrode of the first MOS tube is coupled with the second end of the first active inductor, a source electrode of the first MOS tube is coupled with the current source, a grid electrode of the first MOS tube is used as a first input end of the amplifying module, and The second input unit comprises a second MOS tube, the drain electrode of the second MOS tube is coupled with the second end of the second active inductor, the source electrode of the second MOS tube is coupled with the current source, and the grid electrode of the second MOS tube is used as the second input end of the amplifying module; When the first power supply end is a power supply anode, the first MOS tube and the second MOS tube are NMOS tubes, and when the second power supply end is a power supply anode, the first MOS tube and the second MOS tube are PMOS tubes.
  4. 4. The equalizer of claim 2, wherein: The first active inductor comprises a third MOS tube and a first resistor, wherein the source electrode of the third MOS tube is coupled with the first power end, the drain electrode of the third MOS tube is coupled with the first end of the first input unit, the first end of the first resistor is coupled with the grid electrode of the third MOS tube, the second end of the first resistor is coupled with the drain electrode of the third MOS tube, and The second active inductor comprises a fourth MOS tube and a second resistor, the source electrode of the fourth MOS tube is coupled with the first power end, the drain electrode of the fourth MOS tube is coupled with the first end of the second input unit, the first end of the second resistor is coupled with the grid electrode of the fourth MOS tube, and the second end of the second resistor is coupled with the drain electrode of the fourth MOS tube; The third MOS tube and the fourth MOS tube are PMOS tubes when the first power end is a power anode and the second power end is a power cathode, and are NMOS tubes when the first power end is a power cathode and the second power end is a power anode.
  5. 5. The equalizer of claim 4, wherein the first resistor and the second resistor are adjustable resistors, and the adjustable resistors adjust resistance based on an external tuning signal.
  6. 6. The equalizer of claim 4, wherein: The first resistor is a fifth MOS tube, the second resistor is a sixth MOS tube, and the resistance values of the fifth MOS tube and the sixth MOS tube are adjusted based on external tuning signals; the fifth MOS tube and the sixth MOS tube are PMOS tubes or NMOS tubes.
  7. 7. The equalizer of any one of claims 4-6, wherein the bias current module comprises: the first end of the first bias current unit is coupled with the grid electrode of the third MOS tube, and the second end of the first bias current unit is coupled with the second power supply end; and the first end of the second bias current unit is coupled with the grid electrode of the fourth MOS tube, and the second end of the second bias current unit is coupled with the second power supply end.
  8. 8. The equalizer of claim 7, wherein: the first bias current unit comprises a seventh MOS tube, the drain electrode of the seventh MOS tube is coupled with the grid electrode of the third MOS tube, the source electrode is coupled with the second power supply end, the grid electrode receives bias voltage, and The second bias current unit comprises an eighth MOS tube, the drain electrode of the eighth MOS tube is coupled with the grid electrode of the fourth MOS tube, the source electrode of the eighth MOS tube is coupled with the second power supply end, and the grid electrode receives the bias voltage; The seventh MOS tube and the eighth MOS tube are NMOS tubes when the first power end is a power anode and the second power end is a power cathode, and are PMOS tubes when the first power end is a power cathode and the second power end is a power anode.
  9. 9. The equalizer of claim 7, wherein the bias current module further comprises: a first capacitor having a first end coupled to the gate of the third MOS transistor and a second end coupled to the drain of the fourth MOS transistor, and And the first end of the second capacitor is coupled with the grid electrode of the fourth MOS tube, and the second end of the second capacitor is coupled with the drain electrode of the third MOS tube.
  10. 10. A chip comprising the equalizer according to claim 1 to 9.

Description

Equalizer and chip Technical Field The present invention relates to the field of integrated circuits, and in particular, to an equalizer and a chip. Background An Equalizer (Equalizer) is an electronic device capable of adjusting the amplification of electric signals of various frequency components, and has a core function of compensating for attenuation in a channel or frequency defects in a playback system by adjusting the gain (boost or attenuation) of signals of different frequencies, thereby improving signal quality or sound effect. The equalizer is widely applied to the field of audio (such as sound equipment, sound console and music playing software) and communication systems (such as digital communication and cable television), and is an indispensable signal processing tool in two types of scenes. Fig. 1 shows an equalizer structure comprising four transistors (denoted Q1, Q2, Q3, Q4), a current source Is and two resistors (denoted Ra and Rb), wherein the transistor Q3 and the resistor Ra form one set of active inductors, and the transistor Q4 and the resistor Rb form the other set of active inductors. The scheme utilizes the active inductor to amplify the high-frequency signal, but loses the low-frequency gain, and meanwhile, the gain amplitude of the high-frequency signal is limited. Therefore, how to ensure a high-frequency gain amplitude without losing a low-frequency gain and to ensure a sufficient high-frequency signal gain has become one of the problems to be solved by those skilled in the art. It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present invention and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the invention section. Disclosure of Invention In view of the above drawbacks of the prior art, an object of the present invention is to provide an equalizer and a chip for solving the problems that the high-frequency gain and the low-frequency gain of the equalizer cannot be compatible, and the amplitude of the high-frequency gain is limited in the prior art. To achieve the above and other related objects, the present invention provides an equalizer including at least: The amplifying module amplifies the input high-frequency signal based on the active inductor; And the bias current module is coupled with the active inductor in the amplifying module and provides bias current for the active inductor. Optionally, the amplifying module includes a first active inductor, a second active inductor, a first input unit, a second input unit and a current source; the first end of the first active inductor is coupled with a first power end, and the second end of the first active inductor is coupled with the first end of the first input unit and serves as a first output end of the amplifying module; the first end of the second active inductor is coupled with the first power end, and the second end of the second active inductor is coupled with the first end of the second input unit and serves as a second output end of the amplifying module; The second end of the first input unit and the second end of the second input unit are coupled with a second power end through the current source, and the input ends of the first input unit and the second input unit are used as differential input ends; The first power end and the second power end are respectively arranged as a power anode and a power cathode. More optionally, the first input unit comprises a first MOS transistor having a drain coupled to the second end of the first active inductor, a source coupled to the current source, and a gate as the first input end of the amplifying module, and The second input unit comprises a second MOS tube, the drain electrode of the second MOS tube is coupled with the second end of the second active inductor, the source electrode of the second MOS tube is coupled with the current source, and the grid electrode of the second MOS tube is used as the second input end of the amplifying module; When the first power supply end is a power supply anode, the first MOS tube and the second MOS tube are NMOS tubes, and when the second power supply end is a power supply anode, the first MOS tube and the second MOS tube are PMOS tubes. More optionally, the first active inductor comprises a third MOS transistor and a first resistor, wherein the source electrode of the third MOS transistor is coupled with the first power supply end, the drain electrode of the third MOS transistor is coupled with the first end of the first input unit, the first end of the first resistor is coupled with the grid electrode of the third MOS transistor, the second end of the first resistor is coupled with the drain electrode of the third MOS transistor, an