CN-122026817-A - Digital down-conversion implementation method based on FPGA+ADC

CN122026817ACN 122026817 ACN122026817 ACN 122026817ACN-122026817-A

Abstract

The invention relates to a digital down-conversion implementation method based on FPGA+ADC, belonging to the technical field of laser radar. The digital down-conversion algorithm is transferred from the FPGA to the ADC, so that the running power consumption of the whole chip can be reduced, the difficulty of layout and wiring among boards can be reduced, the data processing capacity of the FPGA can be reduced, and the resource consumption of the FPGA can be further saved.

Inventors

CHEN BOYANG
ZHU GE
WANG HAO
FENG ZHENZHONG
LI SHAOBO
LI YUHANG
TONG WENHAO
LUO ZHENBAO
WU ZHONGJIAN
Lv Mingai
TIAN WENFEI
ZHAO JINGTONG
YU CHEN
LIU XUNSU

Assignees

西南技术物理研究所

Dates

Publication Date: 20260512
Application Date: 20251230

Claims (10)

1. The digital down-conversion implementation method based on the FPGA and the ADC is characterized in that the method is implemented based on the FPGA and the acquisition sub-card, wherein the FPGA and the acquisition sub-card are both positioned on the board card, the acquisition sub-card is the ADC, and the ADC can work in a digital down-conversion DDC extraction mode; the FPGA comprises a clock chip LMK04828, a configuration module, a JESD204B demapping module and a data processing module, wherein the configuration module is used for configuring the working mode of the acquisition sub-card into a digital down-conversion DDC extraction mode, the clock chip LMK04828 is used for determining the clock signal of the FPGA, and the method comprises the following steps: After the board card is powered on or reset, an SPI interface is adopted at the FPGA end to configure a clock chip LMK04828 and a configuration module, so that the acquisition sub-card works in a DDC extraction mode; Step two, the acquisition sub-card works in a DDC extraction mode to sample data; Step three, a JESD204B link is established between the acquisition sub-card and the JESD204B demapping module, and the JESD204B demapping module decodes the sampled data after receiving the sampled data from the acquisition sub-card and then sends the decoded sampled data to the data processing module; and step four, the data processing module performs Fourier transformation on the decoded data to obtain the spectrum characteristics of the extracted data.
2. The method of claim 1, wherein in the second step, the matlab is used to simulate and generate the 75MHZ to-be-sampled signal and the 250MHZ sinusoidal signal, and then the acquisition sub-card is used to sample the to-be-sampled signal with the simulated and generated 250MHZ sinusoidal signal.
3. The method of claim 1, wherein 2,4, 8, 16 times data sampling is achieved by gating the four half-band filters, respectively, when the ADC is operating at a preset sampling rate.
4. The method of claim 1, wherein the digital down conversion method comprises NCO, half-band decimation filtering, FIR filtering, gain processing, and complex-to-real conversion.
5. A method as in claim 1, wherein said JESD204B link is established over a JESD204B bus.
6. The method of claim 1, wherein the frequency of the signal to be sampled is reduced after digital down conversion.
7. The method of claim 1, wherein the method is used in a lidar.
8. A system for implementing the method of any one of claims 1 to 7.
9. The system of claim 8, wherein the system is used in a lidar.
10. Use of a method according to any of claims 1 to 7 in lidar signal processing.

Description

Digital down-conversion implementation method based on FPGA+ADC Technical Field The invention belongs to the technical field of laser radars, and particularly relates to a digital down-conversion implementation method based on FPGA+ADC. Background At present, in a data acquisition module of a laser radar, a high-speed analog-to-digital converter (ADC) is generally adopted to realize conversion from an analog signal to a digital signal, and then data interaction between an acquisition card and an FPGA is completed through a high-speed interface based on JESD204B protocol. When the ADC sampling rate is higher, the data transmission rate is increased, the layout and wiring requirements of the board are more strict, and in addition, the time sequence control at the FPGA end is not easy due to the increase of the clock frequency of the logic system. Disclosure of Invention First, the technical problem to be solved The invention aims to solve the technical problem of designing a digital down-conversion implementation method and saving the resource consumption of an FPGA. (II) technical scheme In order to solve the technical problems, the invention provides a digital down-conversion implementation method based on FPGA and ADC, which is implemented based on FPGA and acquisition sub-cards, wherein the FPGA and the acquisition sub-cards are both positioned on a board card, the acquisition sub-card is ADC, and the ADC can work in a digital down-conversion DDC extraction mode; the FPGA comprises a clock chip LMK04828, a configuration module, a JESD204B demapping module and a data processing module, wherein the configuration module is used for configuring the working mode of the acquisition sub-card into a digital down-conversion DDC extraction mode, the clock chip LMK04828 is used for determining the clock signal of the FPGA, and the method comprises the following steps: After the board card is powered on or reset, an SPI interface is adopted at the FPGA end to configure a clock chip LMK04828 and a configuration module, so that the acquisition sub-card works in a DDC extraction mode; Step two, the acquisition sub-card works in a DDC extraction mode to sample data; Step three, a JESD204B link is established between the acquisition sub-card and the JESD204B demapping module, and the JESD204B demapping module decodes the sampled data after receiving the sampled data from the acquisition sub-card and then sends the decoded sampled data to the data processing module; and step four, the data processing module performs Fourier transformation on the decoded data to obtain the spectrum characteristics of the extracted data. (III) beneficial effects The invention has the following beneficial effects: First, because the bottom layer of the FPGA is provided with a large number of digital circuit processing units, when the DDC algorithm result is processed, not only can the 'pipeline' operation be realized, but also multiple multiplication operations can be performed in parallel, so that the data 'blocking' is avoided, the calculation time is saved, and the running performance of the system is improved. Secondly, the extraction and filtering of different data rates can be simply and rapidly realized in the ADC, and the digital down-conversion algorithm is transferred from the FPGA to the ADC, so that the whole running power consumption of the chip can be reduced, the difficulty of the layout and wiring between boards can be reduced, the data processing capacity of the FPGA can be reduced, and the resource consumption of the FPGA can be further saved. Drawings FIG. 1 is a diagram of a digital down-conversion DDC structure of the present invention; FIG. 2 is a block diagram of a system design of the present invention; FIG. 3 is a diagram of the process of the present invention for generating an original signal in matlab and sampling with a high frequency signal; FIG. 4 is a spectrum characteristic diagram obtained by performing digital down-conversion processing on a sampled signal in matlab and then performing FFT operation; FIG. 5 is a waveform diagram of data obtained after the AD9680 implements the DDC algorithm; Fig. 6 is a spectrum characteristic diagram obtained by performing FFT on data extracted by the AD 9680. Detailed Description For the purposes of clarity, content, and advantages of the present invention, a detailed description of the embodiments of the present invention will be described in detail below with reference to the drawings and examples. The invention provides a digital down-conversion implementation method based on FPGA+ADC, which is implemented based on FPGA and acquisition sub-card ADC, wherein the FPGA and the acquisition sub-card ADC are both positioned on a board card, and the ADC works in a digital down-conversion DDC extraction mode. As shown in fig. 1, the digital down-conversion method includes NCO, half-band decimation filtering, FIR filtering, gain processing, and complex-to-real conversion. When t