CN-122026825-A - Band gap reference source circuit

CN122026825ACN 122026825 ACN122026825 ACN 122026825ACN-122026825-A

Abstract

The invention relates to the technical field of wireless communication, and provides a band gap reference source circuit, which comprises a first gain enhancement circuit, a second gain enhancement circuit, a third gain enhancement circuit, an operational amplifier, a first voltage sampling circuit, a second voltage sampling circuit, a third voltage sampling circuit and a buffer circuit, wherein the first gain enhancement circuit is connected with the first voltage sampling circuit; the first voltage sampling circuit controls the magnitude of the output gain of the first gain enhancement circuit according to the bias voltage, the second voltage sampling circuit controls the magnitude of the output gain of the second gain enhancement circuit according to the bias voltage, the third voltage sampling circuit controls the magnitude of the output gain of the third gain enhancement circuit according to the bias voltage, the operational amplifier receives the gain output by the second gain enhancement circuit through the non-inverting input end and outputs an enhancement gain signal after being amplified in phase, and the operational amplifier receives the gain output by the first gain enhancement circuit through the inverting input end. The band-gap reference source circuit can improve the voltage suppression ratio of the high-frequency power supply.

Inventors

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Assignees

深圳飞骧科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260413

Claims (10)

1. The band gap reference source circuit is characterized by comprising a first gain enhancement circuit, a second gain enhancement circuit, a third gain enhancement circuit, an operational amplifier, a first voltage sampling circuit, a second voltage sampling circuit, a third voltage sampling circuit and a buffer circuit; The first end of the first gain enhancement circuit is connected with the first end of the second gain enhancement circuit, the first end of the third gain enhancement circuit and the first end of the buffer circuit respectively and is commonly used for connecting a power supply, and the second end of the first gain enhancement circuit is connected with the second end of the second gain enhancement circuit, the second end of the third gain enhancement circuit, the second end of the buffer circuit and the output end of the operational amplifier respectively; the third end of the first gain enhancement circuit is connected with the first end of the first voltage sampling circuit, the second end of the first voltage sampling circuit is respectively connected with the second end of the second voltage sampling circuit, the second end of the third voltage sampling circuit and the third end of the buffer circuit, the third end of the first voltage sampling circuit is respectively connected with the third end of the second voltage sampling circuit, the third end of the third voltage sampling circuit and the fourth end of the buffer circuit and is grounded, the fourth end of the first voltage sampling circuit is respectively connected with the fourth end of the first gain enhancement circuit and the inverting input end of the operational amplifier, the fourth end of the second voltage sampling circuit is respectively connected with the fourth end of the second gain enhancement circuit and the non-inverting input end of the operational amplifier, the fourth end of the third gain enhancement circuit is connected with the fourth end of the third voltage sampling circuit and is used for outputting a reference voltage, the fourth end of the buffer circuit is also used for connecting an external control logic circuit, and the external logic circuit is respectively used for sampling the voltage of the first voltage sampling circuit and the fourth voltage sampling circuit, the third voltage sampling circuit and the buffer circuit provide bias voltages; The first voltage sampling circuit controls the output gain of the first gain enhancement circuit according to the bias voltage, the second voltage sampling circuit controls the output gain of the second gain enhancement circuit according to the bias voltage, the third voltage sampling circuit controls the output gain of the third gain enhancement circuit according to the bias voltage, the operational amplifier receives the output gain of the second gain enhancement circuit through a non-inverting input end and outputs an enhancement gain signal after amplifying the same phase, the operational amplifier receives the output gain of the first gain enhancement circuit through an inverting input end and outputs a reduction gain signal after amplifying the same phase, and the buffer circuit is used for realizing voltage buffering on the third voltage sampling circuit.
2. The bandgap reference source circuit of claim 1, wherein said first gain enhancement circuit comprises a first MOS transistor, a second MOS transistor and a third MOS transistor; The source electrode of the first MOS tube is connected with the source electrode of the third MOS tube and is used as the first end of the first gain enhancement circuit, the grid electrode of the first MOS tube is used as the second end of the first gain enhancement circuit, the drain electrode of the first MOS tube is respectively connected with the source electrode of the second MOS tube and the grid electrode of the third MOS tube, the grid electrode of the second MOS tube is connected with the drain electrode of the third MOS tube and is used as the third end of the first gain enhancement circuit, and the drain electrode of the second MOS tube is used as the fourth end of the first gain enhancement circuit.
3. The bandgap reference source circuit of claim 2, wherein said second gain enhancement circuit comprises a fourth MOS transistor, a fifth MOS transistor and a sixth MOS transistor; The source electrode of the fourth MOS tube is connected with the source electrode of the sixth MOS tube and is used as the first end of the second gain enhancement circuit, the grid electrode of the fourth MOS tube is used as the second end of the second gain enhancement circuit, the drain electrode of the fourth MOS tube is respectively connected with the source electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube, the grid electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube and is used as the third end of the second gain enhancement circuit, and the drain electrode of the fifth MOS tube is used as the fourth end of the second gain enhancement circuit.
4. The bandgap reference circuit of claim 3, wherein said third gain enhancement circuit comprises a seventh MOS transistor, an eighth MOS transistor and a ninth MOS transistor; The source electrode of the seventh MOS tube is connected with the source electrode of the ninth MOS tube and is used as the first end of the third gain enhancement circuit, the grid electrode of the seventh MOS tube is used as the second end of the third gain enhancement circuit, the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the eighth MOS tube and the grid electrode of the ninth MOS tube, the grid electrode of the eighth MOS tube is connected with the drain electrode of the ninth MOS tube and is used as the third end of the third gain enhancement circuit, and the drain electrode of the eighth MOS tube is used as the fourth end of the third gain enhancement circuit.
5. The bandgap reference circuit of claim 4, wherein said first to ninth MOS transistors are PMOS transistors.
6. The bandgap reference source circuit of claim 1, wherein said buffer circuit comprises a tenth MOS transistor and an eleventh MOS transistor; The source electrode of the tenth MOS tube is used as the first end of the buffer circuit, the grid electrode of the tenth MOS tube is used as the second end of the tenth MOS tube, the drain electrode of the tenth MOS tube is connected with the drain electrode of the eleventh MOS tube, the source electrode of the eleventh MOS tube is used as the fourth end of the buffer circuit and is grounded, and the drain electrode of the eleventh MOS tube is connected with the grid electrode of the eleventh MOS tube and is used as the third end of the buffer circuit.
7. The bandgap reference source circuit of claim 1, wherein said first voltage sampling circuit comprises a twelfth MOS transistor and a first triode; The drain electrode of the twelfth MOS tube is used as the first end of the first voltage sampling circuit, the grid electrode of the twelfth MOS tube is used as the second end of the first voltage sampling circuit, the source electrode of the twelfth MOS tube is respectively connected with the base electrode of the first triode and the collector electrode of the first triode and used as the third end of the first voltage sampling circuit, and the emitter electrode of the first triode is used as the fourth end of the first voltage sampling circuit.
8. The bandgap reference circuit of claim 7, wherein said second voltage sampling circuit includes a thirteenth MOS transistor, a second triode and a first resistor; The drain electrode of the thirteenth MOS tube is used as the first end of the second voltage sampling circuit, the grid electrode of the thirteenth MOS tube is used as the second end of the second voltage sampling circuit, the source electrode of the thirteenth MOS tube is respectively connected with the base electrode of the second triode and the collector electrode of the second triode and used as the third end of the second voltage sampling circuit, the emitter electrode of the second triode is connected with the first end of the first resistor, and the second end of the first resistor is used as the fourth end of the second voltage sampling circuit.
9. The bandgap reference circuit of claim 8, wherein said third voltage sampling circuit comprises a fourteenth MOS transistor, a third triode and a second resistor; The drain electrode of the fourteenth MOS tube is used as the first end of the third voltage sampling circuit, the grid electrode of the fourteenth MOS tube is used as the second end of the third voltage sampling circuit, the source electrode of the fourteenth MOS tube is respectively connected with the base electrode of the third triode and the collector electrode of the third triode and used as the third end of the third voltage sampling circuit, the emitter electrode of the third triode is connected with the first end of the second resistor, and the second end of the second resistor is used as the fourth end of the third voltage sampling circuit.
10. The bandgap reference circuit of claim 9, wherein said twelfth MOS transistor, said thirteenth MOS transistor and said fourteenth MOS transistor are NMOS transistors.

Description

Band gap reference source circuit Technical Field The invention relates to the technical field of wireless communication, in particular to a band gap reference source circuit. Background The bandgap reference source is a basic module of a core in an Analog integrated circuit or a mixed signal system, and key indexes such as temperature stability, voltage rejection ratio (Power Supply Rejection Ratio, PSRR), precision and the like of output voltage directly determine the overall performance of electronic systems such as Digital-to-Analog Converter (DAC), analog-to-Digital Converter (ADC), low dropout linear voltage regulator (Low Dropout Regulator, LDO), radio frequency transceiver and the like. Along with the development of semiconductor technology and the expansion of application scenes of electronic equipment, portable, low-power-consumption and high-precision electronic equipment has higher requirements on the performance of a band gap reference source, and particularly, the voltage suppression ratio is used as a core parameter for measuring the power supply noise suppression capability of the reference source, and the advantages and disadvantages of the voltage suppression ratio directly influence the anti-interference capability and the output precision of a system, so that the voltage suppression ratio becomes an important direction for the technical development of the band gap reference source. The traditional band gap reference source realizes reference voltage output by means of a temperature compensation principle of band gap voltage, but a core amplifying tube and a load tube in a classical structure adopt a single-stage MOS tube structure, and power noise is easily directly transmitted to an output end through channel coupling of the MOS tube, so that PSRR performance is limited. In order to break through the bottleneck, the industry proposes to upgrade a single-stage tube structure into a cascode (cascode) structure, and increase the suppression path of power supply noise by adding device stacking, so that the single-stage tube structure becomes a main stream improvement thought for improving the PSRR of the band gap reference source. The invention focuses on the optimization and promotion of the PSRR of the band gap reference source, and provides a technical scheme with practicability aiming at the defects of the traditional structure and the existing cascade improved structure. In the related art, as shown in fig. 1, the conventional bandgap reference source adopts a classical bandgap core architecture, and mainly comprises an operational amplifier (Operational Amplifier, OP), a MOS transistor (M1/M2/M3), a bipolar transistor (BJT) (Q1/Q2/Q3) and a resistor R1/R2. The temperature compensation circuit comprises a temperature compensation core device, an operational amplifier, a current mirror and a voltage source, wherein M1 and M2 are differential pair tubes, M3 is an output reference voltage tube, Q1 and Q2 are temperature compensation core devices, BJTs with different emitter areas are used for generating voltage differences positively correlated with temperature, temperature compensation is realized through a resistor network in combination with band gap voltages negatively correlated with the temperature, the reference voltage VREF with zero temperature coefficient is output, the operational amplifier works in a negative feedback closed loop state, collector voltages of Q1 and Q2 are forced to be equal, and the gate source voltages of M1 and M2 are guaranteed to be consistent, so that the accurate matching of the current mirror is realized. However, the traditional band gap reference source architecture only depends on a single-stage MOS tube to realize current mirror and signal transmission, and power supply noise can be directly coupled to an output end through a gate source/drain source capacitor of the MOS tube, so that the voltage suppression ratio performance is extremely poor. In order to improve the voltage suppression ratio of the conventional structure, as shown in fig. 2, the prior art upgrades the single-stage MOS transistor structure to a cascode structure, and newly adds a cascode transistor M4/M5/M6 to the source/drain paths of the MOS transistors M1, M2, M3, M4, M2-M5, M3-M6 to form a three-stage stacked structure. The feedback node of the operational amplifier is separated from the grid bias node of the common-source common-gate tube, so that the temperature compensation core logic of the traditional band-gap reference source is reserved, and only the architecture of the core amplifying and load tube is upgraded. However, in the prior art, an M4/M5/M6 cascode structure is newly added, and an independent bias voltage VB is required to be introduced, so that the design complexity and the power consumption of the bias circuit are increased. The additional bias module not only improves the chip area and the power consumption cost, but also needs to additionally design a bias