Search

CN-122026833-A - Unilateral current detection amplifier circuit, chip and electronic equipment

CN122026833ACN 122026833 ACN122026833 ACN 122026833ACN-122026833-A

Abstract

The disclosure relates to the technical field of circuits, in particular to a unilateral current detection amplifier circuit, a chip and electronic equipment, wherein the unilateral current detection amplifier circuit comprises an operational amplifier op, an enhanced PMOS tube MPF 1 , an enhanced PMOS tube MPL 1 , an enhanced PMOS tube MPF 2 , an enhanced PMOS tube MPL 2 , a resistor R la , a resistor R lb , a resistor R da , a resistor R db , a resistor R S , a buffer BUF 1 and a buffer BUF 2 . According to the unilateral current detection amplifier circuit in the technical scheme provided by the embodiment of the disclosure, the two sets of circuits of the high-side circuit and the low-side circuit are not required to be switched, and bidirectional current sampling can be realized through one set of circuit, so that the circuit scale is reduced, more chip area is not required to be occupied when the circuits are integrated, and the design and manufacturing cost is reduced.

Inventors

  • SHEN HONGWEI
  • MA YAN
  • BAI ZHIHUA
  • MA YONGWANG
  • WEN LIGUO
  • ZHEN SHAOWEI

Assignees

  • 北京智芯微电子科技有限公司
  • 电子科技大学

Dates

Publication Date
20260512
Application Date
20251229

Claims (10)

  1. 1. The unilateral current detection amplifier circuit is characterized by comprising an operational amplifier op, an enhanced PMOS tube MPF 1 , an enhanced PMOS tube MPL 1 , an enhanced PMOS tube MPF 2 , an enhanced PMOS tube MPL 2 , a resistor R la , a resistor R lb , a resistor R da , a resistor R db , a resistor R S , a buffer BUF 1 and a buffer BUF 2 ; One end of the resistor R S is connected with one end of the resistor R da and the common-mode voltage end V cm1 , the other end of the resistor R S is connected with one end of the resistor R db and the common-mode voltage end V cm2 , the other end of the resistor R da is connected with the non-inverting input end V+ of the operational amplifier op and the drain of the enhanced PMOS tube MPF 1 , the other end of the resistor R db is connected with the inverting input end V-of the operational amplifier op and the drain of the enhanced PMOS tube MPF 2 , the homodromous output end V O+ of the operational amplifier op is connected with the gate of the enhanced PMOS tube MPF 1 and the gate of the enhanced PMOS tube MPL 1 , the inverting output end V O- of the operational amplifier op is connected with the gate of the enhanced PMOS tube MPF 2 and the gate of the enhanced PMOS tube MPL 2 , the source of the enhanced PMOS tube MPF 1 , the source electrode of the enhanced PMOS tube MPL 1 , The source of the enhanced PMOS tube MPL 2 and the source of the enhanced PMOS tube MPL 2 are both connected to the input voltage terminal V DD , the drain of the enhanced PMOS tube MPL 1 is connected to one end of the resistor R la and the unidirectional input terminal of the buffer BUF 1 , the other end of the resistor R la is grounded GND, the drain of the enhanced PMOS tube MPL 2 is connected to one end of the resistor R lb and the unidirectional input terminal of the buffer BUF 2 , the other end of the resistor R lb is grounded GND, the reverse input terminal of the buffer BUF 1 is connected to the output terminal B out1 of the buffer BUF 1 , the power supply terminal of the buffer BUF 1 is connected to the input voltage terminal V DD , the reverse input terminal of the buffer BUF 2 is connected to the output terminal B out2 of the buffer BUF 2 , and the power supply terminal of the buffer BUF 2 is connected to the input voltage terminal V DD .
  2. 2. The single-sided current sense amplifier circuit of claim 1, wherein the operational amplifier op comprises a current amplifying unit, a biasing unit, a main circuit unit, and a common mode feedback circuit unit; the first end of the current amplifying unit is connected with the non-inverting input end V+ of the operational amplifier op, the second end of the current amplifying unit is connected with the inverting input end V-of the operational amplifier op, the third end of the current amplifying unit is connected with the first end of the main circuit unit, and the fourth end of the current amplifying unit is connected with the second end of the main circuit unit; The first end of the biasing unit is connected with the third end of the main circuit unit; The fourth end of the main circuit unit is connected with the first end of the common mode feedback circuit unit, the fifth end of the main circuit unit is connected with the second end of the common mode feedback circuit unit, and the sixth end of the main circuit unit is connected with the third end of the common mode feedback circuit unit; The fourth end of the common mode feedback circuit unit is connected with the homodromous output end V O+ of the operational amplifier op, and the fifth end of the common mode feedback circuit unit is connected with the reverse output end V O- of the operational amplifier op.
  3. 3. The single-sided current sense amplifier circuit of claim 2, wherein the current amplifying unit comprises an NPN transistor Q N1 , an NPN transistor Q N2 , an NPN transistor Q N3 , an NPN transistor Q N4 , an enhancement PMOS transistor M P1 , an enhancement PMOS transistor M P2 , a resistor R 2a , and a resistor R 2b ; Wherein, the first end of the current amplifying unit is connected with the emitter of the NPN type triode Q N1 and the emitter of the NPN type triode Q N2 , the second end of the current amplifying unit is connected with the emitter of the NPN type triode Q N3 and the emitter of the NPN type triode Q N4 , the base electrode of the NPN type triode Q N1 , the base electrode of the NPN triode Q N2 , the collector electrode of the NPN triode Q N2 , the base electrode of the NPN triode Q N3 , The collector of the NPN triode Q N3 and the base of the NPN triode Q N4 are connected with the drain of the enhanced PMOS tube M P2 , the collector of the NPN triode Q N1 is connected with one end of a resistor R 2a and the fourth end of the current amplifying unit, the collector of the NPN triode Q N4 is connected with one end of the resistor R 2b and the third end of the current amplifying unit, the source of the enhanced PMOS tube M P2 is connected with the drain of the enhanced PMOS tube M P1 , the grid of the enhanced PMOS tube M P2 is connected with an external bias voltage end V B4 , the grid of the enhanced PMOS tube M P1 is connected with an external bias voltage end V B3 , the other end of the resistor R 2a is connected with a third end of the current amplifying unit, The other end of the resistor R 2b and the source electrode of the enhanced PMOS tube M P1 are connected with the input voltage end V DD .
  4. 4. The single-sided current sense amplifier circuit of claim 3, wherein the bias unit comprises an enhancement NMOS transistor M N1 , an enhancement NMOS transistor M N2 , an enhancement PMOS transistor M P11 , a PNP transistor Q 3 , a resistor R 2c , a resistor R 3a , and a resistor R 3b ; The source of the enhanced NMOS tube M N1 and one end of the resistor R 3a are grounded GND, the other end of the resistor R 3a is connected with the drain of the enhanced PMOS tube M P11 , the gate of the enhanced NMOS tube M N1 is connected with an external bias voltage end V B1 , the drain of the enhanced NMOS tube M N1 is connected with the source of the enhanced NMOS tube M N2 , the gate of the enhanced NMOS tube M N2 is connected with the external bias voltage end V B2 , the drain of the enhanced NMOS tube M N2 is connected with the gate of the enhanced PMOS tube M P11 and the collector of the PNP type triode Q 3 , the source of the enhanced PMOS tube M P11 is connected with the base of the PNP type triode Q 3 , One end of the resistor R 3b and the first end of the biasing unit are connected, the emitter of the PNP triode Q 3 is connected with one end of the resistor R 2c , and the other end of the resistor R 3b is connected with the other end of the resistor R 2c and the input voltage end V DD .
  5. 5. The single-sided current sense amplifier circuit of claim 4, wherein the resistance of the resistor R 2a is the same as the resistance of the resistor R 2b , and the resistance of the resistor R 2a and the resistance of the resistor R 2b are half the resistance of the resistor R 2c .
  6. 6. The single-sided current sense amplifier circuit of claim 4, wherein the main circuit unit comprises PNP transistor Q 1 , PNP transistor Q 2 , enhancement NMOS transistor M N3 , enhancement NMOS transistor M N4 , enhancement NMOS transistor M N5 , enhancement NMOS transistor M N6 , enhancement NMOS transistor M N7 , enhancement NMOS transistor M N8 , enhancement PMOS transistor M P3 , enhancement PMOS transistor M P4 , enhancement PMOS transistor M P5 , enhancement PMOS transistor M P6 , enhancement PMOS transistor M P7 , enhancement PMOS transistor M P8 , capacitor C M1 , and capacitor C M2 ; Wherein, the source of the enhanced NMOS tube M N3 , the source of the enhanced NMOS tube M N4 , The source of the enhancement NMOS transistor M N7 and the source of the enhancement NMOS transistor M N8 are grounded to GND, the gate of the enhancement NMOS transistor M N3 and the gate of the enhancement NMOS transistor M N4 are connected to the sixth terminal of the main circuit unit, the drain of the enhancement NMOS transistor M N3 is connected to the collector of the PNP transistor Q 1 and the source of the enhancement NMOS transistor M N5 , the drain of the enhancement NMOS transistor M N4 is connected to the collector of the PNP transistor Q 2 and the source of the enhancement NMOS transistor M N6 , the base of the PNP transistor Q 1 and the base of the PNP transistor Q 2 are connected to the third terminal of the main circuit unit, the emitter of the PNP transistor Q 1 is connected to the first terminal of the main circuit unit, the emitter of the PNP transistor Q 2 is connected to the second terminal of the main circuit unit, the drain of the enhancement NMOS transistor M N5 and the drain of the enhancement NMOS transistor M N6 are connected to the drain of the enhancement NMOS transistor M N6 , and the drain of the enhancement NMOS transistor M B2 is connected to the external bias transistor M8654 The grid electrode of the enhanced PMOS tube M P8 and one end of the capacitor C M2 are connected, the drain electrode of the enhanced NMOS tube M N6 is connected with the drain electrode of the enhanced PMOS tube M P6 , The grid of the enhanced PMOS tube M P7 and one end of the capacitor C M1 are connected, the grid of the enhanced PMOS tube M P5 and the grid of the enhanced PMOS tube M P6 are connected with an external bias voltage end V B4 , the source of the enhanced PMOS tube M P5 is connected with the drain of the enhanced PMOS tube M P3 , the source of the enhanced PMOS tube M P6 is connected with the drain of the enhanced PMOS tube M P4 , the grid of the enhanced PMOS tube M P3 and the grid of the enhanced PMOS tube M P4 are connected with an external bias voltage end V B3 , the grid of the enhanced NMOS tube M N7 and the grid of the enhanced NMOS tube M N8 are connected with an external bias voltage end V B1 , the drain of the enhanced NMOS tube M N7 is connected with the other end of the capacitor C M1 , The drain electrode of the enhanced PMOS tube M P7 is connected with the fourth end of the main circuit unit, the drain electrode of the enhanced NMOS tube M N8 is connected with the other end of the capacitor C M2 , the drain electrode of the enhanced PMOS tube M P8 and the fifth end of the main circuit unit, the source electrode of the enhanced PMOS tube M P3 , The source of the enhanced PMOS transistor M P4 , the source of the enhanced PMOS transistor M P7 , and the source of the enhanced PMOS transistor M P8 are connected to the input voltage terminal V DD .
  7. 7. The single-sided current sense amplifier circuit of claim 6, wherein the common mode feedback circuit unit comprises an enhanced NMOS transistor M N9 , an enhanced PMOS transistor M P9 , and an enhanced PMOS transistor M P10 ; The source of the enhanced NMOS transistor M N9 is grounded GND, the drain of the enhanced NMOS transistor M N9 , the gate of the enhanced NMOS transistor M N9 , the drain of the enhanced PMOS transistor M P9 , and the drain of the enhanced PMOS transistor M P10 are all connected to the third terminal of the common mode feedback circuit unit, the gate of the enhanced PMOS transistor M P9 is connected to the first terminal of the common mode feedback circuit unit and the fourth terminal of the common mode feedback circuit unit, the gate of the enhanced PMOS transistor M P10 is connected to the second terminal of the common mode feedback circuit unit and the fifth terminal of the common mode feedback circuit unit, and the source of the enhanced PMOS transistor M P9 and the source of the enhanced PMOS transistor M P10 are all connected to the input voltage terminal VDD.
  8. 8. The single-sided current sense amplifier circuit of claim 7, wherein the external bias voltage terminal V B1 is configured to output a first gate bias voltage, the first gate bias voltage being configured to operate the enhancement NMOS transistor M N1 , the enhancement NMOS transistor M N7 , and the enhancement NMOS transistor M N8 in a saturation region; The external bias voltage terminal V B2 is configured to output a second gate bias voltage, where the second gate bias voltage is configured to make the enhancement NMOS transistor M N2 , the enhancement NMOS transistor M N5 , and the enhancement NMOS transistor M N6 all operate in a saturation region; The external bias voltage terminal V B3 is configured to output a third gate bias voltage, where the third gate bias voltage is configured to make the enhancement PMOS transistor M P1 , the enhancement PMOS transistor M P3 , and the enhancement PMOS transistor M P4 all operate in a saturation region; The external bias voltage terminal V B4 is configured to output a fourth gate bias voltage, where the fourth gate bias voltage is configured to make the enhancement PMOS transistor M P2 , the enhancement PMOS transistor M P5 , and the enhancement PMOS transistor M P6 all operate in a saturation region.
  9. 9. A chip comprising the single-sided current sense amplifier circuit of any one of claims 1-8.
  10. 10. An electronic device, characterized in that, the electronic device comprising the chip of claim 9.

Description

Unilateral current detection amplifier circuit, chip and electronic equipment Technical Field The disclosure relates to the technical field of circuits, in particular to a unilateral current detection amplifier circuit, a unilateral current detection amplifier chip and electronic equipment. Background Accurate measurement of current is a fundamental requirement of modern electronic systems, and is widely used in the fields of power management, battery monitoring, motor control, industrial automation, and the like. As a key element in these systems, a Current sense amplifier (Current SENSE AMPLIFIER, CSA) can achieve high-precision Current monitoring by converting the small voltage drop across the shunt resistor into an amplified anti-noise voltage signal. In the related art, in order to implement bidirectional current sampling, a common-mode voltage varying in a wide range needs to be handled by the current detection amplifying circuit, and thus the current detection amplifying circuit generally includes a circuit structure with two complementary sides, i.e., a high-side circuit and a low-side circuit. When the common-mode voltage is higher, the high-side circuit is closed, the low-side circuit works normally, and when the common-mode voltage is lower, the high-side circuit is normal, and the low-side circuit is closed. However, such a design results in a larger scale of the current sense amplifier circuit, which occupies more chip area if the circuit is integrated, resulting in higher design and manufacturing costs. Disclosure of Invention In order to solve the problems in the related art, embodiments of the present disclosure provide a single-side current detection amplifier circuit, a chip, and an electronic device. In a first aspect, an embodiment of the disclosure provides a unilateral current detection amplifier circuit, which comprises an operational amplifier op, an enhanced PMOS tube MPF 1, an enhanced PMOS tube MPL 1, an enhanced PMOS tube MPF 2, an enhanced PMOS tube MPL 2, a resistor R la, a resistor R lb, a resistor R da, a resistor R db, a resistor R S, a buffer BUF 1, and a buffer BUF 2; One end of a resistor R S is connected with one end of a resistor R da and a common-mode voltage end V cm1, the other end of the resistor R S is connected with one end of a resistor R db and a common-mode voltage end V cm2, the other end of the resistor R da is connected with an in-phase input end V+ of an operational amplifier op and a drain electrode of an enhanced PMOS tube MPF 1, the other end of the resistor R db is connected with an opposite-phase input end V-of the operational amplifier op and a drain electrode of an enhanced PMOS tube MPF 2, a homodromous output end V O+ of the operational amplifier op is connected with a grid electrode of an enhanced PMOS tube MPF 1 and a grid electrode of an enhanced PMOS tube MPL 1, an opposite output end V O- of the operational amplifier op is connected with a grid electrode of an enhanced PMOS tube MPF 2 and a grid electrode of an enhanced PMOS tube MPL 2, a source electrode of an enhanced PMOS tube MPF 1, a source electrode of the enhanced PMOS tube MPL 1, the source of the enhanced PMOS tube MPL 2 and the source of the enhanced PMOS tube MPL 2 are both connected with an input voltage end V DD, the drain of the enhanced PMOS tube MPL 1 is connected with one end of a resistor R la and the same-direction input end of a buffer BUF 1, the other end of the resistor R la is grounded GND, the drain of the enhanced PMOS tube MPL 2 is connected with one end of a resistor R lb and the same-direction input end of a buffer BUF 2, the other end of the resistor R lb is grounded GND, the reverse input end of the buffer BUF 1 is connected with an output end B out1 of a buffer BUF 1, the power end of the buffer BUF 1 is connected with an input voltage end V DD, the reverse input end of the buffer BUF 2 is connected with an output end B out2 of the buffer BUF 2, and the power end of the buffer BUF 2 is connected with the input voltage end V DD. In one embodiment of the present disclosure, the operational amplifier op includes a current amplifying unit, a bias unit, a main circuit unit, and a common mode feedback circuit unit; the first end of the current amplifying unit is connected with the non-inverting input end V+ of the operational amplifier op, the second end of the current amplifying unit is connected with the inverting input end V-of the operational amplifier op, the third end of the current amplifying unit is connected with the first end of the main circuit unit, and the fourth end of the current amplifying unit is connected with the second end of the main circuit unit; the first end of the biasing unit is connected with the third end of the main circuit unit; The fourth end of the main circuit unit is connected with the first end of the common mode feedback circuit unit, the fifth end of the main circuit unit is connected with the second end of the common mode feedb