CN-122026842-A - Gain amplifying circuit, control method and amplifying chip

CN122026842ACN 122026842 ACN122026842 ACN 122026842ACN-122026842-A

Abstract

The application discloses a gain amplifying circuit, a control method and an amplifying chip, and belongs to the field of gain amplification. The first branch comprises a first input end, a first output end, a first amplifying element, a first adjusting element array and a second adjusting element array, the second branch comprises a second input end, a second output end, a second amplifying element, a third adjusting element array and a fourth adjusting element array, the first end of the first amplifying element is electrically connected to the first input end, the second end of the first amplifying element is grounded, the first end of the first adjusting element array and the first end of the second adjusting element array are both electrically connected to the third end of the first amplifying element, the second end of the first adjusting element array is electrically connected to the first output end, the second end of the second adjusting element array is electrically connected to the second output end, and the first end of the second amplifying element is electrically connected to the second input end.

Inventors

LIU ZICHENG
LI ZHIKAI
LIU MAOZHI
CHEN YUHANG
LIU KAI

Assignees

重庆北理芯研科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260130

Claims (10)

1. The gain amplifying circuit is characterized by comprising a first branch and a second branch; The first branch comprises a first input end, a first output end, a first amplifying element, a first adjusting element array and a second adjusting element array, and the second branch comprises a second input end, a second output end, a second amplifying element, a third adjusting element array and a fourth adjusting element array; The first end of the first amplifying element is electrically connected to the first input end, the second end of the first amplifying element is grounded, the first end of the first adjusting element array and the first end of the second adjusting element array are both electrically connected to the third end of the first amplifying element, the second end of the first adjusting element array is electrically connected to the first output end, the second end of the second adjusting element array is electrically connected to the second output end, the first end of the second amplifying element is electrically connected to the second input end, the second end of the second amplifying element is grounded, the first end of the third adjusting element array and the first end of the fourth adjusting element array are both electrically connected to the third end of the second amplifying element, the second end of the third adjusting element array is electrically connected to the first output end, and the second end of the fourth adjusting element array is electrically connected to the second output end; The first adjusting element array, the second adjusting element array, the third adjusting element array and the fourth adjusting element array all comprise an adjusting resistor and at least one adjusting MOS tube, and the adjusting resistor is connected with at least one adjusting MOS tube in parallel.
2. The gain amplification circuit of claim 1, wherein the resistance of the tuning resistors in the first tuning element array, the resistance of the tuning resistors in the second tuning element array, the resistance of the tuning resistors in the third tuning element array, and the resistance of the tuning resistors in the fourth tuning element array are all equal.
3. The gain amplification circuit of claim 2, wherein the number of adjustment MOS transistors in the first array of adjustment elements, the number of adjustment MOS transistors in the second array of adjustment elements, the number of adjustment MOS transistors in the third array of adjustment elements, and the number of adjustment MOS transistors in the fourth array of adjustment elements are all equal.
4. The gain amplification circuit of claim 3, wherein the number of adjustment MOS transistors in the first array of adjustment elements, the number of adjustment MOS transistors in the second array of adjustment elements, the number of adjustment MOS transistors in the third array of adjustment elements, and the number of adjustment MOS transistors in the third array of adjustment elements are all multiple; the MOS transistor array comprises a first adjusting element array, a second adjusting element array, a third adjusting element array, a fourth adjusting element array and a third adjusting element array, wherein a plurality of adjusting MOS transistors are connected in parallel, the sizes of the adjusting MOS transistors are different, a plurality of adjusting MOS transistors in the first adjusting element array are connected in parallel, two adjusting MOS transistors in the fourth adjusting element array are connected in parallel, and two adjusting MOS transistors in the fourth adjusting element array are different.
5. The gain amplification circuit of claim 4, wherein the sizes of the plurality of adjustment MOS transistors in the first adjustment element array, the sizes of the plurality of adjustment MOS transistors in the second adjustment element array, the sizes of the plurality of adjustment MOS transistors in the third adjustment element array, and the sizes of the plurality of adjustment MOS transistors in the fourth adjustment element array all increase in sequence in a parallel direction; the size of any one of the adjusting MOS transistors in the first adjusting element array is equal to the size of the adjusting MOS transistor in the second adjusting element array, the size of the adjusting MOS transistor in the third adjusting element array and the size of the adjusting MOS transistor in the fourth adjusting element array.
6. The gain amplification circuit of claim 1, wherein the first array of tuning elements, the second array of tuning elements, the third array of tuning elements, and the fourth array of tuning elements each comprise 1 tuning resistor and 4 tuning MOS transistors, and 4 tuning MOS transistors are connected in parallel, and the tuning resistor is connected in parallel with 4 tuning MOS transistors.
7. The gain amplification circuit of any one of claims 1-6, wherein the first amplification element and the second amplification element are amplification MOS transistors, and wherein the amplification MOS transistors are different in size from the adjustment MOS transistors.
8. A control method for controlling the gain amplification circuit of any one of claims 1-7, wherein the first array of adjustment elements, the second array of adjustment elements, the third array of adjustment elements, and the fourth array of adjustment elements each comprise a plurality of adjustment MOS transistors, the control method comprising: Under the condition that the current output by the gain amplification circuit needs to be regulated, the gain amplification circuit is switched to a regulating state from an initial state, wherein the initial state is that all regulating MOS (metal oxide semiconductor) tubes in the first regulating element array and all regulating MOS tubes in the fourth regulating element array are in a conducting state, all regulating MOS tubes in the second regulating element array and all regulating MOS tubes in the third regulating element array are in a disconnecting state, the regulating state is that at least one regulating MOS tube in the first regulating element array is in a disconnecting state, all regulating MOS tubes in the rest are in a conducting state, at least one regulating MOS tube in the second regulating element array is in a conducting state, all regulating MOS tubes in the third regulating element array are in a disconnecting state, and at least one regulating MOS tube in the fourth regulating element array is in a disconnecting state, all regulating MOS tubes in the rest are in a conducting state.
9. The control method according to claim 8, wherein in the adjustment state, the number of the adjustment MOS transistors in the first adjustment element array in the off state, the number of the adjustment MOS transistors in the second adjustment element array in the on state, the number of the adjustment MOS transistors in the third adjustment element array in the on state, and the number of the adjustment MOS transistors in the fourth adjustment element array in the off state are all equal.
10. An amplifying chip, characterized in that the amplifying chip comprises the gain amplifying circuit according to any one of claims 1 to 7.

Description

Gain amplifying circuit, control method and amplifying chip Technical Field The present application relates to the field of gain amplification technologies, and in particular, to a gain amplifying circuit, a control method, and an amplifying chip. Background When the current is adjusted by the gain amplification circuit, that is, when the gain of the gain amplification circuit is amplified, it is desirable to change only the magnitude of the current and not the phase of the current. But in an actual circuit the current phase varies with the gain. In the related art, the current phase is generally corrected by adding an inductance to the gain amplification circuit, through the inductance. However, by increasing the inductance, the gain amplification circuit is larger in size, which is disadvantageous in that the size of a chip including the gain amplification circuit is reduced. Disclosure of Invention The application aims to provide a gain amplifying circuit, a control method and an amplifying chip, which at least solve the problem that the size of the gain amplifying circuit is larger by increasing inductance, thereby being unfavorable for reducing the size of the chip containing the gain amplifying circuit. In order to solve the technical problems, the application is realized as follows: In a first aspect, an embodiment of the present application provides a gain amplification circuit, including a first branch and a second branch; The first branch comprises a first input end, a first output end, a first amplifying element, a first adjusting element array and a second adjusting element array, and the second branch comprises a second input end, a second output end, a second amplifying element, a third adjusting element array and a fourth adjusting element array; the first end of the first amplifying element is electrically connected to the first input end, the second end of the first amplifying element is grounded, the first end of the first adjusting element array and the first end of the second adjusting element array are both electrically connected to the third end of the first amplifying element, the second end of the first adjusting element array is electrically connected to the first output end, and the second end of the second adjusting element array is electrically connected to the second output end; The first end of the second amplifying element is electrically connected to the second input end, the second end of the second amplifying element is grounded, the first end of the third adjusting element array and the first end of the fourth adjusting element array are both electrically connected to the third end of the second amplifying element, the second end of the third adjusting element array is electrically connected to the first output end, and the second end of the fourth adjusting element array is electrically connected to the second output end; The first adjusting element array, the second adjusting element array, the third adjusting element array and the fourth adjusting element array all comprise an adjusting resistor and at least one adjusting MOS tube, and the adjusting resistor is connected with at least one adjusting MOS tube in parallel. Optionally, the resistance of the adjusting resistor in the first adjusting element array, the resistance of the adjusting resistor in the second adjusting element array, the resistance of the adjusting resistor in the third adjusting element array, and the resistance of the adjusting resistor in the fourth adjusting element array are all equal. Optionally, the number of the adjusting MOS transistors in the first adjusting element array, the number of the adjusting MOS transistors in the second adjusting element array, the number of the adjusting MOS transistors in the third adjusting element array, and the number of the adjusting MOS transistors in the fourth adjusting element array are all equal. Optionally, the number of the adjusting MOS transistors in the first adjusting element array, the number of the adjusting MOS transistors in the second adjusting element array, the number of the adjusting MOS transistors in the third adjusting element array, and the number of the adjusting MOS transistors in the third adjusting element array are all multiple; the MOS transistor array comprises a first adjusting element array, a second adjusting element array, a third adjusting element array, a fourth adjusting element array and a third adjusting element array, wherein a plurality of adjusting MOS transistors are connected in parallel, the sizes of the adjusting MOS transistors are different, a plurality of adjusting MOS transistors in the first adjusting element array are connected in parallel, two adjusting MOS transistors in the fourth adjusting element array are connected in parallel, and two adjusting MOS transistors in the fourth adjusting element array are different. Optionally, the sizes of the plurality of adjustment MOS transistors in the first adjust