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CN-122026862-A - Power consumption adjusting method for generating test excitation by automatic test pattern

CN122026862ACN 122026862 ACN122026862 ACN 122026862ACN-122026862-A

Abstract

The invention relates to a power consumption adjusting method for generating test excitation of an automatic test pattern, which comprises the following steps of providing a test register module, analyzing the distribution condition of a clock gating unit (ICG) in an integrated circuit, and dynamically controlling an enabling signal of the ICG through the test register module based on the analysis result of the ICG distribution condition so as to realize the power consumption adjustment of the ATPG test excitation of the automatic test pattern generation. The invention realizes the power consumption adjusting method of ATPG test excitation by dynamically controlling the clock gating unit enabling signal, and solves the problems of yield reduction, poor traditional threshold adjusting effect and the like caused by overhigh test power consumption.

Inventors

  • LIU YONGBO
  • JIANG WENLI

Assignees

  • 奕行智能科技(广州)有限公司
  • 奕行智能科技(南京)有限公司
  • 奕算智能科技(上海)有限公司

Dates

Publication Date
20260512
Application Date
20260204

Claims (10)

  1. 1. A method for power consumption adjustment for automatic test pattern generation test stimulus, comprising the steps of: Providing a test register module; Analyzing distribution of clock gating cells ICG in an integrated circuit, and Based on the analysis result of the ICG distribution situation, the enabling signal of the ICG is dynamically controlled through the test register module, so that the power consumption adjustment of automatic test pattern generation ATPG test excitation is realized.
  2. 2. The method of power consumption adjustment for automatic test pattern generation test stimulus of claim 1, wherein the test register module is configured to output a preset binary signal to control an enable of an ICG.
  3. 3. The method for power consumption adjustment for automatic test pattern generation test stimulus according to claim 1, wherein the test register module is simple in configuration and easy to reconstruct, and the method for providing the test register module comprises: Selecting D-type trigger with reset function and D-type trigger with set function, and And automatically generating the test register module through a Python script, wherein the input parameters of the Python script comprise a D-type trigger type with a reset function, a D-type trigger type with a set function and a parameter configuration list, and the name and the default value of each register are recorded in the parameter configuration list.
  4. 4. The method for adjusting power consumption of automatic test pattern generation test stimulus according to claim 3, wherein the D-type flip-flop with reset function and the D-type flip-flop with set function are standard cells in a cell library.
  5. 5. The method for power consumption adjustment for automatic test pattern generation test stimulus according to claim 1, wherein analyzing the distribution of ICGs includes: The number of ICGs in the target clock domain and the number of registers fanned out by each ICG are counted from the clock domain dimension to estimate the test power consumption of the region.
  6. 6. The method for power consumption adjustment for automatic test pattern generation test stimulus according to claim 1, wherein analyzing the distribution of ICGs includes: the number of ICGs under each design level and the number of registers fanned out by each ICG are counted from the design level dimension to refine the analysis of the power consumption distribution.
  7. 7. The method for adjusting power consumption of automatic test pattern generation test stimulus according to claim 1, wherein dynamically controlling an enable signal of an ICG by the test register module based on an analysis result of ICG distribution conditions, comprises: when the manner of dynamically controlling the enable signal of the ICG is clock domain control, the method comprises the following steps: outputting a target control signal through a test register module; Mixing the target control signal with the original functional signal of the integrated circuit to form a final ICG target enabling signal, and The ICG target enabling signal is input to a test enabling end of the ICG in the target clock domain to realize the regional power consumption adjustment.
  8. 8. The method for adjusting power consumption of automatic test pattern generation test stimulus according to claim 1, wherein dynamically controlling an enable signal of an ICG by the test register module based on an analysis result of ICG distribution conditions, comprises: when the manner of dynamically controlling the enable signal of the ICG is design level control, the method comprises the following steps: outputting a target control signal through a test register module; Mixing each path of target control signal with original function signal of integrated circuit respectively, and And correspondingly inputting each mixed signal to a test enabling end of a corresponding ICG in the target design level to realize the level power consumption adjustment.
  9. 9. The method for power consumption adjustment for automatic test pattern generation test stimulus according to claim 1, characterized in that when the manner of dynamically controlling the enable signal of ICG is clock domain and design level mixed control, comprising the steps of: configuring at least two test register modules, wherein a first test register module is responsible for controlling the clock domain dimension and a second test register module is responsible for controlling the design hierarchy dimension, and The first test register module outputs a clock domain control signal, mixes with an original functional signal and inputs the clock domain control signal to an ICG test enabling end corresponding to the clock domain, and the second test register module outputs a design level control signal, mixes with the original functional signal and inputs the design level ICG test enabling end corresponding to the design level, so that the joint power consumption adjustment of the clock domain and the design level is realized.
  10. 10. The method for adjusting power consumption of automatic test pattern generation test stimulus according to claim 1, wherein the preset binary signal is 0 or 1, and dynamic switching of ICG enabled state is achieved by adjusting the preset binary signal.

Description

Power consumption adjusting method for generating test excitation by automatic test pattern Technical Field The invention relates to the technical field of integrated circuit testing, in particular to a power consumption adjusting method for Automatic TEST PATTERN Generation (ATPG) test excitation, which is simple and efficient and can dynamically adapt to a chip circuit structure by dynamically controlling a clock gating unit enabling signal. Background In the production and testing links of integrated circuits (INTEGRATED CIRCUIT, ICs), ATPG technology is one of the core means for guaranteeing the chip yield, which simulates the working scenario of a chip by generating specific test excitation signals to detect whether the chip has design defects or manufacturing faults. However, ATPG test stimulus is faced with the technical pain point of too high power consumption in practical application, namely, the signal turnover rate of the test stimulus is far higher than the normal working state of a chip, so that the local power consumption of the chip is suddenly increased in the test process, the problems of chip overheating, signal integrity reduction and the like are easily caused, the test result of automatic test equipment (Automatic Test Equipment, ATE) exceeds the range of the preset technical Specification (Specification, spec), and a large number of chips which are required to be qualified are finally misjudged as 'disqualified (Fail'), and the IC yield (INTEGRATED CIRCUIT YIELD ) is further reduced. Aiming at the problem, the prior art mainly relies on adjusting the Threshold (Threshold) parameter of an ATPG tool to limit the power consumption of test excitation, but the mode can only make indirect constraint from the level of 'test excitation generation rule', cannot match the actual circuit structure and power consumption distribution of a chip, has very limited effect of improving the actual power consumption in the test process, and meanwhile, the coverage of the test excitation is reduced due to the fact that the Threshold is excessively adjusted, the detection of partial faults is omitted, the test reliability is further influenced, and the method has little significance on the actual power consumption. Disclosure of Invention The invention provides a power consumption adjusting method for generating test excitation by automatic test patterns, in particular to a power consumption adjusting method for realizing ATPG test excitation by dynamically controlling a clock gating unit enabling signal, which solves the technical problems of Yield (YIeld) reduction, poor traditional threshold value adjusting effect and the like caused by overhigh test power consumption, and simultaneously balances test coverage and circuit realization complexity. The invention provides a power consumption adjusting method for automatically generating test excitation by a test pattern, which comprises the following steps: Providing a test register module; Analyzing distribution of clock gating cells ICG in an integrated circuit, and Based on the analysis result of the ICG distribution situation, an enable signal of the ICG is dynamically controlled through the test register module so as to realize the power consumption adjustment of generating ATPG test excitation by the automatic test pattern. Further, the test register module is configured to output a preset binary signal to control an enable terminal of the ICG. Further, the test register module is simple in configuration and easy to reconstruct, and the test register module is provided, comprising: Selecting D-type trigger with reset function and D-type trigger with set function, and The test register module is automatically generated through a Python script, namely, a hardware description language code (Verilog code) of the test register module is automatically generated, input parameters of the Python script comprise a D-type trigger type with a reset function, a D-type trigger type with a set function and a parameter configuration list, and the name and the default value of each register are recorded in the parameter configuration list. Further, the D-type trigger with the reset function and the D-type trigger with the set function are standard units in an element library. Further, analyzing the distribution of ICGs includes: The number of ICGs in the target clock domain and the number of registers fanned out by each ICG are counted from the clock domain dimension to estimate the test power consumption of the region. Further, analyzing the distribution of ICGs includes: the number of ICGs under each design level and the number of registers fanned out by each ICG are counted from the design level dimension to refine the analysis of the power consumption distribution. Further, based on the analysis result of the ICG distribution situation, dynamically controlling, by the test register module, an enable signal of the ICG, including: when the manner of dynamically contr