CN-122026864-A - Pulse latch trigger and data latch method

CN122026864ACN 122026864 ACN122026864 ACN 122026864ACN-122026864-A

Abstract

The application discloses a pulse latch trigger and a data latch method. The pulse latch trigger comprises a master latch and a slave latch, wherein the master latch and the slave latch are connected in cascade, a sampling signal of input data is provided at an internal node between the master latch and the slave latch, output data is provided at an output end of the slave latch, and a pulse generator is used for generating a gating signal according to the input data and the output data and controlling data sampling and data updating of the master latch and the slave latch, wherein the pulse generator adopts logic operation of the sampling signal and the output data to realize indirect comparison of the input data and the output data, and a trigger pulse of the gating signal is generated according to a comparison result. The master-slave latch can meet the time sequence constraint condition, so that the reliability of data latching is improved and the working frequency is improved.

Inventors

CHEN XIANGDONG
SONG WEIQUAN
ZHUO CHENG
ZHAO QIYONG
ZHANG LI
CHEN ZHENGRUI

Assignees

杭州士兰微电子股份有限公司
杭州湃力芯科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260410

Claims (20)

1. A pulse latch flip-flop comprising: A master latch comprising a master latch and a slave latch connected in cascade, a sampling signal providing input data at an internal node between the master latch and the slave latch, and output data at an output of the slave latch, and A pulse generator for generating a gate signal for controlling data sampling and data updating of the master-slave latch according to the sampling signal and the output data, The pulse generator adopts the logic operation of the sampling signal and the output data to realize the indirect comparison of the input data and the output data, and generates the trigger pulse of the gating signal according to the comparison result.
2. The pulse latch flip-flop of claim 1, wherein the pulse generator comprises: the logic module is used for carrying out logic operation on the sampling signal and the output data so as to generate a comparison signal; a holding module for generating an intermediate pulse signal based on the comparison signal and selectively holding a predetermined level state of the intermediate pulse signal, and And the shaping module is used for shaping the intermediate pulse signal to generate the gating signal.
3. The pulse latch flip-flop of claim 2, wherein the hold module switches the follow mode and the hold mode according to a system clock, or The holding module switches a following mode and a holding mode according to an inverted signal of the intermediate pulse signal.
4. The pulse latch flip-flop of claim 3 wherein, In the following mode, the intermediate pulse signal follows the comparison signal, In the hold mode, the intermediate pulse signal changes its level state in response to a predetermined edge of the comparison signal, and maintains the predetermined level state until the hold mode ends when the level state is the predetermined level state.
5. A pulse latch flip-flop according to claim 3, wherein the pulse generator generates a trigger pulse of the gating signal on a rising edge of the system clock.
6. The pulse latch flip-flop of claim 5, wherein the logic block is an exclusive or gate and the shaping block is a nand gate.
7. The pulse latch flip-flop of claim 6, wherein the logic module comprises: A first transmission gate turned on to transmit an inverted signal of the output data when the sampling signal is not valid, and And a second transmission gate which is turned on to transmit the output data when the sampling signal is active.
8. The pulse latch flip-flop of claim 5, wherein the hold module comprises: A first transistor, a second transistor and a third transistor connected in series between a power supply terminal and ground, the first transistor and the third transistor being connected as an inverter in the following mode, the third transistor being a pull-down transistor in the holding mode, and A fourth transistor and a fifth transistor connected in series between an output terminal of the holding module and ground, a ground path of the output terminal of the holding module via the fourth transistor and the fifth transistor being turned off in the following mode, and a ground path of the output terminal of the holding module via the fourth transistor and the fifth transistor being turned on according to an inverted signal of the intermediate pulse signal in the holding mode, thereby selectively maintaining a low level state of the intermediate pulse signal.
9. The pulse latch flip-flop according to claim 8, wherein the first transistor to the third transistor are sequentially connected, and an intermediate node of the second transistor and the third transistor is connected to an output terminal of the holding block, The gates of the first transistor and the third transistor receive the comparison signal, and the gate of the second transistor receives the system clock.
10. The pulse latch flip-flop of claim 9, wherein the shaping module multiplexes the fifth transistor, a gate of the fifth transistor receiving the system clock.
11. The pulse latch flip-flop of claim 8, wherein said second transistor, said first transistor and said third transistor are sequentially connected, and wherein an intermediate node of said first transistor and said third transistor is connected to an output of said holding block, The gates of the first transistor and the third transistor receive the comparison signal, and the gate of the second transistor receives an inverted signal of the intermediate pulse signal.
12. The pulse latch flip-flop of claim 11, wherein the shaping module multiplexes the second transistor and multiplexes the fifth transistor, a gate of the fifth transistor receiving the system clock.
13. A pulse latch flip-flop according to claim 3, wherein the pulse generator generates a trigger pulse of the gating signal on a falling edge of the system clock.
14. The pulse latch flip-flop of claim 13, wherein the logic block is an exclusive or gate and the shaping block is a nor gate.
15. The pulse latch flip-flop of claim 14, wherein the logic module comprises: a first transmission gate turned on when the sampling signal is active to transmit an inverted signal of the output data, and And a second transmission gate which is turned on to transmit the output data when the sampling signal is not valid.
16. The pulse latch flip-flop of claim 15, wherein the hold module comprises: A first transistor, a second transistor and a third transistor connected in series between a power supply terminal and ground, the first transistor and the third transistor being connected as an inverter in the following mode, the first transistor being a pull-up transistor in the holding mode, and A fourth transistor and a fifth transistor connected in series between a power supply terminal and an output terminal of the holding module, in which a power supply path of the output terminal of the holding module via the fourth transistor and the fifth transistor is turned off in the following mode, and in which the power supply path of the output terminal of the holding module via the fourth transistor and the fifth transistor is turned on according to an inverted signal of the intermediate pulse signal, thereby selectively maintaining a high level state of the intermediate pulse signal.
17. The pulse latch flip-flop of claim 16, wherein said first transistor through said third transistor are connected in sequence, and wherein an intermediate node of said first transistor and said second transistor is connected to an output of said holding block, The gates of the first transistor and the third transistor receive the comparison signal, and the gate of the second transistor receives an inverted signal of the intermediate pulse signal.
18. The pulse latch flip-flop of claim 17, wherein the shaping module multiplexes the fourth transistor, a gate of the fourth transistor receiving the system clock.
19. The pulse latch flip-flop of claim 16, wherein said first transistor, said third transistor and said second transistor are connected in sequence, and wherein an intermediate node of said first transistor and said third transistor is connected to an output of said holding block, The gates of the first transistor and the third transistor receive the comparison signal, and the gate of the second transistor receives an inverted signal of the intermediate pulse signal.
20. The pulse latch flip-flop of claim 19, wherein the shaping module multiplexes the second transistor and multiplexes the fourth transistor, a gate of the fourth transistor receiving the system clock.

Description

Pulse latch trigger and data latch method Technical Field The application relates to the technical field of digital integrated circuits, in particular to a pulse latch trigger with low power consumption and a data latch method thereof. Background The flip-flop is used as a basic timing unit in a digital integrated circuit and has a decisive influence on the area, power consumption and speed of a chip. Along with the continuous miniaturization of semiconductor process nodes, the traditional master-slave trigger is difficult to meet the requirements of ultra-low power consumption and ultra-high speed application due to the fact that the clock network is large in load and the internal nodes are frequently turned over. To reduce dynamic power consumption, the industry has proposed Pulsed-LATCH FLIP-Flop. The structure samples data by replacing a global clock signal with a narrow pulse signal, and only triggers operation when the data changes, thereby effectively reducing the overall switching activity. The existing pulse latch flip-flop still has various problems. The addition of circuitry to avoid the drain pulse introduces additional transistors that not only promote static power consumption, but also diminish the potential advantages in area and energy efficiency. In addition, the common double-edge triggering mechanism needs to perform sampling on both rising and falling edges of the clock, and still brings about a certain dynamic power consumption. Meanwhile, the pulse width is easily affected by process deviation, voltage fluctuation and temperature variation (PVT), so that the holding time is illegal or the pulse width is insufficient, and the reliability of data latching is severely restricted. In a further improved pulse latch trigger design, a pulse trigger signal is generated based on an edge recognition mechanism of a dynamic topology structure so as to realize a single edge trigger function. The dynamic topology directly compares input data with output data. The improved pulse latch flip-flop has stringent requirements on the hold time of the input data, i.e. the input data must remain stable for a period of time after the active edge of the clock signal until the output data is correctly updated and fed back to the comparison circuit. The excessive hold time requirements of the pulse latch flip-flop design on the input data lead to significant Timing pressures in the design in high frequency scenarios, as clock frequencies rise, timing budgets (Timing budgets) become extremely tight, and this additional hold time burden can squeeze the available propagation time of the combinational logic, become a bottleneck on the critical path, and even lead to Timing violations, limiting the highest operating frequency that the circuit can reach. Disclosure of Invention In view of the above-mentioned technical problems in the prior art, an object of the present invention is to provide a pulse latch flip-flop and a data latch method thereof, wherein an indirect comparison between input data and output data is realized by using node signals inside a master latch and a slave latch, and a predetermined level state of an intermediate pulse signal is selectively maintained to conform to a timing constraint condition, thereby improving reliability of data latch and increasing a working frequency. According to one aspect of the invention, a pulse latch trigger is provided, comprising a master latch and a slave latch which are connected in cascade, wherein a sampling signal of input data is provided at an internal node between the master latch and the slave latch, output data is provided at an output end of the slave latch, and a pulse generator is used for generating a gating signal according to the sampling signal and the output data and controlling data sampling and data updating of the master latch and the slave latch, wherein the pulse generator adopts logic operation of the sampling signal and the output data to realize indirect comparison of the input data and the output data, and generates a trigger pulse of the gating signal according to a comparison result. Optionally, the pulse generator comprises a logic module for carrying out logic operation on the sampling signal and the output data to generate a comparison signal, a holding module for generating an intermediate pulse signal according to the comparison signal and selectively holding a preset level state of the intermediate pulse signal, and a shaping module for shaping the intermediate pulse signal to generate the gating signal. Optionally, the holding module switches the following mode and the holding mode according to a system clock, or the holding module switches the following mode and the holding mode according to an inverted signal of the intermediate pulse signal. Optionally, in the following mode, the intermediate pulse signal follows the comparison signal, in the holding mode, the intermediate pulse signal changes its level state in response to a