CN-122026868-A - Ps-level high-precision low-jitter arbitrary waveform delay device and method

CN122026868ACN 122026868 ACN122026868 ACN 122026868ACN-122026868-A

Abstract

The invention relates to the field of signal generation and time delay, and discloses a ps-level high-precision low-jitter arbitrary waveform delay device and a ps-level high-precision low-jitter arbitrary waveform delay method, wherein the device comprises a delay coarse adjustment module, a delay coarse adjustment module and a delay fine adjustment module, wherein the delay coarse adjustment module is used for receiving an input signal and providing first-level delay; the delay fine adjustment module is coupled to the output end of the delay coarse adjustment module and is used for providing second-stage fine delay on the basis of the first-stage delay, the delay fine adjustment module comprises a plurality of switching devices and physical delay lines corresponding to the switching devices, and the logic control module is respectively connected with the delay coarse adjustment module and the delay fine adjustment module in a communication mode and is used for receiving delay control instructions and controlling the delay coarse adjustment module and the delay fine adjustment module to achieve target total delay.

Inventors

DONG LIZHI
LUO YANG
LIU QING
ZHU WEIGUO

Assignees

中电科思仪科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260109

Claims (10)

1. A ps-level high-precision low-jitter arbitrary waveform delay device, comprising: a delay coarse tuning module for receiving an input signal and providing a first stage delay, the delay coarse tuning module including at least one digital delay chip; A delay fine adjustment module coupled to an output of the delay coarse adjustment module for providing a second stage fine delay based on the first stage delay, the delay fine adjustment module comprising a plurality of switching devices and a physical delay line corresponding to each of the switching devices; The logic control module is respectively in communication connection with the delay coarse adjustment module and the delay fine adjustment module and is used for receiving a delay control instruction and controlling the delay coarse adjustment module and the delay fine adjustment module to achieve target total delay; Wherein the range and step of the first stage delay provided by the coarse delay adjustment module is greater than the second stage fine delay provided by the fine delay adjustment module, the two cooperating to achieve a wide range, high accuracy delay adjustment.
2. The apparatus of claim 1, wherein the coarse delay adjustment module employs a MC100EP196B digital delay chip or a cascade structure thereof, and the monolithic delay range is 2.2-12.4 ns.
3. The apparatus of claim 2, wherein the digital delay chip is delay controlled by a data bus d10:d0, a minimum delay control pin SETMIN, and a maximum delay control pin SETMAX, wherein SETMIN and SETMAX have a higher priority than the data bus d10:d0.
4. The apparatus of claim 1, wherein the delay fine adjustment module comprises N cascaded switching devices, each switching device corresponding to two signal paths, one being a pass-through path and the other being a delay path to which a physical delay line of a specific length is connected, and wherein different delay paths are selected in combination by controlling states of the switching devices so as to provide the second stage fine delay from 0 to a maximum fine adjustment delay amount in preset fine steps.
5. The apparatus of claim 4, wherein the switching device is a high bandwidth relay or a radio frequency switch, and the relay is a ARJ A4H type double pole double throw microwave relay with an operating frequency of 8GHz and an insertion loss of not more than 0.5dB at 6 GHz.
6. The apparatus of claim 4, wherein the delay fine adjustment module comprises 5 cascaded relays corresponding to delay gear positions of 5ps, 10ps, 20ps, 40ps and 80ps, respectively, and continuous delay adjustment in steps of 5ps in a range of 0 to 155ps is achieved by combined switching.
7. The device of claim 1, wherein the delay line in the delay fine adjustment module adopts a coplanar waveguide structure, the dielectric substrate adopts a rogers RO5880 plate material, and the dielectric constant is 2.20±0.02@10ghz.
8. The apparatus of claim 1, wherein the logic control module comprises: an address configuration unit for setting a unique module address for each delay module; The address identification and decoding unit is coupled to the address configuration unit and is used for receiving a target address sent by the upper computer, comparing the target address with the module address and outputting an enabling signal when the target address and the module address are consistent; A parameter latch unit, coupled to the address recognition and decoding unit and the upper computer data bus, for latching a delay control parameter from the data bus under the control of a clock signal when the enable signal is valid; the driving signal generating unit is coupled to the parameter latching unit and is used for converting the latched delay control parameter into a corresponding driving signal so as to control the state of a switching device in the delay fine-tuning module; and the time sequence control unit is used for providing a unified clock signal for the parameter latch unit and coordinating the time sequence of the address identification and decoding unit, the parameter latch unit and the driving signal generation unit.
9. The apparatus of claim 8, wherein the address configuration unit comprises a dial switch for manually setting the module address; The address identifying and decoding unit comprises a plurality of exclusive OR gates, a plurality of logic AND gates and a plurality of logic AND gates, wherein each exclusive OR gate is used for comparing one bit of the target address with a corresponding bit of the module address and outputting a bit matching signal; the parameter latching unit comprises at least one D trigger for latching the delay control parameter on the rising edge or the falling edge of the clock signal; the driving signal generating unit comprises a darlington tube array and is used for converting logic level signals in the delay control parameters into high current signals required for driving the switching devices.
10. A ps-level high-precision low-jitter arbitrary waveform delay method implemented using the apparatus of any one of claims 1 to 9, comprising the steps of: Step S1, a delay control instruction is received, wherein the instruction comprises a target delay total amount; s2, analyzing and generating corresponding coarse control signals and fine control signals through the logic control module according to the target delay total amount; s3, inputting an input signal into the delay coarse adjustment module, and performing large-range and discrete delay adjustment on the input signal according to the coarse adjustment control signal to obtain a first delay signal; s4, inputting the first delay signal to the delay fine adjustment module, and carrying out small-range continuous stepping delay fine adjustment on the first delay signal according to the fine adjustment control signal to obtain a second delay signal; Step S5, outputting the second delay signal as a delay-adjusted final waveform.

Description

Ps-level high-precision low-jitter arbitrary waveform delay device and method Technical Field The invention relates to the field of signal generation and delay, in particular to a ps-level high-precision low-jitter arbitrary waveform delay device and method. Background The arbitrary waveform generator (Arbitrary Waveform Generator, AWG) is a key instrument in modern electronic test measurements, communication system verification, radar signal simulation and scientific research. The core function is to generate and output user-defined time domain waveforms. In many advanced application scenarios, such as multiple antenna (MIMO) system testing, quantum bit manipulation, ultrafast laser pulse synchronization, timing margin testing of high-speed digital interfaces (such as SerDes), etc., complex waveforms need to be generated, and precise time delay adjustment and synchronization control of waveforms output by a single or multiple channels are required. Such delay adjustment needs to have high accuracy (on the order of picoseconds), low additional jitter, wide delay range, and good signal integrity. Currently, the main technical schemes for realizing hardware delay are mainly classified into three types, namely an optical fiber delay method, a digital delay method and an analog delay line method. Each solution has its own inherent advantages and limitations. Although the optical fiber delay method can provide stable delay and solve the limitation of bandwidth, the optical fiber delay method consumes large volume resources and has relatively complex design. The digital delay method uses special delay chip or carries out high-speed encryption sampling, time domain interpolation and the like in digital baseband, and has programmable delay control and flexible control, but has smaller adaptive bandwidth and relatively limited delay resolution. The delay range of the method for simulating the delay line can be freely set, the group delay flatness is high, the power consumption is low, but the delay time is fixed or can be adjusted only by changing the mechanical modes such as cable length, and the delay is not flexible enough. Currently, there are also some integrated delay line chips or modules on the market, trying to compromise the advantages and disadvantages of the above solutions. However, these products tend to fall into a "dilemma" where one type of chip has a large delay range (up to tens of nanoseconds) but a coarse delay resolution (typically above tens of picoseconds) and another type of chip has a high delay resolution (up to picoseconds) but a very limited delay range (typically less than 1 nanosecond). Thus, the prior art solutions have significant drawbacks in high-end applications that require a combination of a wide delay range (in the order of nanoseconds to ten nanoseconds), high delay accuracy (in the order of picoseconds steps), and very low additional jitter (in the order of subpicoseconds to picoseconds). The optical fiber scheme is heavy, expensive and inflexible, the precision and bandwidth of the pure digital scheme are limited, the pure analog scheme is not programmable, and the existing integrated chip is difficult to meet the requirements in the range and precision at the same time. Disclosure of Invention In order to solve the technical problems, the invention provides a ps-level high-precision low-jitter arbitrary waveform delay device and a ps-level high-precision low-jitter arbitrary waveform delay method, so as to achieve the purpose of realizing wide-range, high-precision and low-jitter arbitrary waveform delay. In order to achieve the above purpose, the technical scheme of the invention is as follows: A ps-level high precision low jitter arbitrary waveform delay device comprising: a delay coarse tuning module for receiving an input signal and providing a first stage delay, the delay coarse tuning module including at least one digital delay chip; A delay fine adjustment module coupled to an output of the delay coarse adjustment module for providing a second stage fine delay based on the first stage delay, the delay fine adjustment module comprising a plurality of switching devices and a physical delay line corresponding to each of the switching devices; The logic control module is respectively in communication connection with the delay coarse adjustment module and the delay fine adjustment module and is used for receiving a delay control instruction and controlling the delay coarse adjustment module and the delay fine adjustment module to achieve target total delay; Wherein the range and step of the first stage delay provided by the coarse delay adjustment module is greater than the second stage fine delay provided by the fine delay adjustment module, the two cooperating to achieve a wide range, high accuracy delay adjustment. In the scheme, the delay coarse adjustment module adopts an MC100EP196B type digital delay chip or a cascade structure, and the single-chip delay range is 2