CN-122026869-A - Multimode clock data recovery method and device using symmetrical jump selection

CN122026869ACN 122026869 ACN122026869 ACN 122026869ACN-122026869-A

Abstract

The invention discloses a multimode clock data recovery method and device using symmetric jump selection, comprising a sampling circuit, jump selection logic and phase detection logic, wherein the sampling circuit is configured to sample data signals, the jump selection logic is configured to identify signal jumps in the sampled data signals, the sampling circuit comprises a group of comparators, the jump selection logic dynamically selects jump subsets which occur between voltage levels symmetric relative to reference voltages, the invention adopts a rising edge and falling edge jump selector which dynamically filters signal jumps, only processes the jumps between symmetrical voltage levels and refuses asymmetrical jumps, in addition, the architecture realizes the sharing of samplers, namely detection logic for specific voltage levels is multiplexed between different modulation modes, and the method obviously reduces the circuit area and the power consumption and improves the jitter performance of recovered clocks.

Inventors

XU ZHENG
ZHAO CHUNHE

Assignees

上海芯浦科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260127

Claims (10)

1. A multimode clock data recovery device utilizing symmetric transition selection comprises a sampling circuit, transition selection logic and phase detection logic, and is characterized in that the sampling circuit is configured to sample data signals, the transition selection logic is configured to identify signal transitions in the sampled data signals, and the sampling circuit comprises a set of comparators.
2. The multimode clock data recovery device utilizing symmetric transition selection of claim 1, wherein the transition selection logic dynamically selects a subset of transitions occurring between voltage levels that are symmetric with respect to a reference voltage.
3. The multimode clock data recovery device utilizing symmetric transition selection of claim 2, wherein the selected subset of transitions is determined based on an active modulation mode of the data signal.
4. The multimode clock data recovery device utilizing symmetric transition selection of claim 1, wherein the phase detection logic is coupled to the transition selection logic for generating the phase error signal for the selected symmetric transition subset.
5. The multimode clock data recovery device utilizing symmetric transition selection of claim 1, wherein at least one comparator of the set of comparators is reconfigurable to detect a first voltage threshold when operating in a first modulation mode and to detect a second voltage threshold when operating in a second modulation mode.
6. The multimode clock data recovery device utilizing symmetric transition selection of claim 1, wherein the transition selection logic is configured to exclude transitions occurring between voltage levels that are asymmetric with respect to a reference voltage, thereby minimizing data dependent jitter in the recovered clock signal.
7. The multimode clock data recovery device utilizing symmetric transition selection of claim 1, further comprising a clock adjustment circuit for adjusting a phase of the sampling clock based on a phase error signal generated by the phase detection logic.
8. The multimode clock data recovery apparatus utilizing symmetric transition selection of claim 7, wherein the clock adjustment circuit is a phase interpolator or a voltage controlled oscillator.
9. The method for recovering multi-mode clock data using symmetric transition selection as set forth in claim 1, wherein the method comprises the steps of: Step one, receiving a data signal modulated according to one of a plurality of selectable modulation modes; Step two, determining an active modulation mode of a data signal; step three, configuring selection criteria based on an active modulation mode to identify effective signal hops; Updating the clock phase based only on the identified valid signal transitions while ignoring transitions between asymmetric voltage levels; And fifth, multiplexing the common sampling resources to detect different signal levels associated with different modulation schemes.
10. The method for multi-mode clock data recovery using symmetric transition selection of claim 9, wherein the active signal transitions are limited to transitions that occur between voltage levels that are symmetric about a center reference.

Description

Multimode clock data recovery method and device using symmetrical jump selection Technical Field The invention relates to a method for realizing a deserializer clock data recovery unit, which is suitable for realizing various universal serial/deserializer (SerDes) Clock Data Recovery (CDR) units, in particular to a multimode clock data recovery method and device using symmetrical jump selection. Background Clock Data Recovery (CDR) is an underlying component in high-speed serial communications, and the prior art has utilized mainly Mueller-Muller (MM) or Bang-Bang (BB) phase detectors to perform time correction on binary data (e.g., NRZ) by detecting the characteristics of rising and falling edges. In the context of high-speed data, the industry has employed high-order pulse amplitude modulation (e.g., PAM4 and PAM 8) to increase bandwidth. Related prior art in this field includes: U.S. patent 10,218,444 (Inphi/Marvell) describes a high speed PAM4 transceiver using Digital Signal Processing (DSP). These systems typically rely on complex architectures to handle multi-level signaling, often requiring significant power consumption to handle all signal hops. The reference emphasizes the industry standard challenge of detecting "all" data transitions while providing high loop gain, which results in excessive power consumption and large circuit area, while the simplified scheme typically suffers from poor jitter performance. The defects of the prior art are as follows: The need to detect rising and falling edges of data transmissions causes specific problems when the conventional MM or BB CDR method described in the prior art is applied to high-order PAM data (such as PAM4 or PAM 8). 1. Firstly, the complexity is too high, namely, tracking all hops can be too complicated, so that the power consumption and the area use of a chip are too large; 2. And secondly, asymmetric jitter, namely, signal jump occurring between asymmetric voltage levels (relative to zero point) can cause the midpoints of rising edges and falling edges of signals to swing leftwards or rightwards relative to the center, and the physical phenomenon introduces significant clock jitter on a clock recovered by CDR, so that accuracy of data sampling is affected. Disclosure of Invention The present invention aims to provide a new method of jitter reduction that explicitly rejects asymmetric hops, distinguishing itself from the cited prior art (e.g. us patent 10,218,444). Unlike conventional CDRs which attempt to process all transitions to maximize phase information, which typically results in data-dependent jitter caused by physical shifts in the edge midpoints in an asymmetric signal, the present apparatus recognizes and exploits only signal transitions that occur between two sets of respectively symmetric voltage levels (e.g., levels +/-15 or +/-5), and by filtering out transitions that are not symmetric across the zero threshold, the present invention essentially eliminates the specific jitter component caused by asymmetric edge shifts. In addition, the invention introduces a novel hardware architecture, and reduces the complexity of the circuit through sharing of the multimode samplers. While conventional multi-standard SerDes designs typically require separate sampling logic or redundant parallel paths for different modulation modes, the present invention employs a rising-edge-falling-transition selector (Edge Transition Selector) that allows hardware resources to be multiplexed. Specifically, the sampler hardware configured to detect the +/-11 voltage threshold during PAM8 or PAM2 operation is reconfigured to detect the +/-5 voltage threshold when the system switches to PAM4 mode. The sharing strategy directly solves the problems of overhigh power consumption and large silicon area existing in the high-order PAM CDR in the prior art. In order to achieve the above purpose, the present invention provides the following technical solutions: A multimode clock data recovery apparatus utilizing symmetric transition selection includes a sampling circuit configured to sample a data signal, transition selection logic configured to identify signal transitions in the sampled data signal, and phase detection logic, the sampling circuit including a set of comparators. As a further aspect of the invention the transition selection logic dynamically selects a subset of transitions that occur between voltage levels that are symmetrical with respect to a reference voltage. As a still further aspect of the invention, the selected subset of hops is determined based on an active modulation mode of the data signal. As a still further aspect of the invention the phase detection logic is coupled to the transition selection logic for generating the phase error signal for the selected symmetric transition subset. As a still further aspect of the invention at least one comparator of the set of comparators is reconfigurable to detect the first voltage threshold when operat