CN-122026870-A - Configurable delay circuit

CN122026870ACN 122026870 ACN122026870 ACN 122026870ACN-122026870-A

Abstract

The application discloses a configurable delay circuit, and relates to the technical field of asynchronous circuit design. The configurable delay circuit comprises a cycle starting module, a cycle module and a cycle judging module, wherein the cycle starting module is used for receiving a signal to be delayed and outputting a cycle starting signal based on the signal to be delayed, the cycle module is used for outputting a cycle judging starting signal based on the cycle starting signal, the cycle judging module is used for receiving a delay periodic signal and determining delay times based on the delay periodic signal, and outputting a cycle ending judging signal after the cycle judging starting signal is delayed based on the delay times, the cycle module is also used for outputting a cycle response signal based on the cycle ending judging signal, and the cycle starting module is also used for resetting the cycle starting signal based on the cycle response signal, overturning the current signal and outputting the delayed signal. The circuit can realize the dynamic adjustment of delay time and reduce the complexity of circuit structure.

Inventors

SHANG DELONG
Cong Jiaxu

Assignees

中国科学院微电子研究所

Dates

Publication Date: 20260512
Application Date: 20241111

Claims (10)

1. A configurable delay circuit, the configurable delay circuit comprising: The circulation starting module is connected with the signal source and used for receiving the signal to be delayed and outputting a circulation starting signal based on the signal to be delayed; the circulation module is connected with the output end of the circulation starting module and is used for outputting a circulation judging starting signal based on the circulation starting signal; The circulation judging module is connected with the output end of the circulation module and an external delay period configuration circuit, and is used for receiving a delay period signal, determining delay times based on the delay period signal, carrying out signal delay on the circulation judging start signal based on the delay times and outputting a circulation ending judging signal; the circulating module is connected with the output end of the circulating judging module and is also used for outputting a circulating response signal based on the circulating ending judging signal; the circulation starting module is connected with the output end of the circulation module, and is further used for resetting the circulation starting signal based on the circulation response signal, overturning the current signal and outputting a delayed signal.
2. The configurable delay circuit of claim 1, wherein the loop initiation module comprises: The pulse generation unit is connected with the signal source and is used for receiving the signal to be delayed and outputting a start pulse signal based on the signal to be delayed; The signal follower unit is connected with the output end of the pulse generation unit, an external starting signal generation circuit, the input end of the circulation module and the output end of the circulation module, and is used for following the starting signal output by the starting signal generation circuit based on the starting pulse signal so as to output the circulation starting signal; And the signal overturning unit is connected with the output end of the circulating module and is used for overturning the current signal based on the circulating response signal so as to output a delayed signal.
3. The configurable delay circuit of claim 2 wherein said pulse generating unit comprises a first delay circuit and an exclusive-or gate, wherein, The input end of the first delay circuit is connected with the signal source, the output end of the first delay circuit is connected with the first input end of the exclusive-or gate, the second input end of the exclusive-or gate is connected with the signal source, and the output end of the exclusive-or gate is connected with the clock input end of the signal following unit; The first delay circuit comprises an even number of inverters connected in series, and is used for delaying the signal to be delayed for a preset time length, so that the exclusive-OR gate outputs a pulse signal with the signal width of the preset time length as the starting pulse signal.
4. The configurable delay circuit of claim 2 wherein the signal follower unit comprises a first D flip-flop, wherein, The data input end of the first D trigger is connected with an external starting signal generating circuit, the clock input end of the first D trigger is connected with the output end of the pulse generating unit, the reset input end of the first D trigger is connected with the output end of the circulating module, and the data output end of the first D trigger is connected with the input end of the circulating module; The first D trigger is used for following the starting signal output by the starting signal generating circuit after receiving the starting pulse signal so as to output the circulating starting signal, and resetting the circulating starting signal after receiving the circulating response signal.
5. The configurable delay circuit of claim 2 wherein the signal flip-flop comprises a first inverter and a second D flip-flop, wherein, The input end of the first inverter is connected with the data output end of the second D trigger, the output end of the first inverter is connected with the data input end of the second D trigger, the clock input end of the second D trigger is connected with the output end of the circulation module, and the data output end of the second D trigger is also used as the output end of the signal overturning unit to output the delayed signal; The first inverter is used for overturning signals of the data output end of the second D trigger, and the second D trigger is used for outputting the signals overturned by the first inverter as the delayed signals after receiving the cyclic response signals.
6. The configurable delay circuit of claim 1, wherein the loop determination module comprises: The signal delay and comparison module is connected with the output end of the circulation module and an external delay period configuration circuit and is used for receiving the delay period signal, carrying out signal delay for a preset time length on a circulation judgment starting signal output by the circulation module, comparing the delay times of the circulation judgment starting signal with the delay period signal and outputting a circulation judgment comparison signal based on a comparison result; The circulation continuation judging module is connected with the output end of the signal delay and comparison module, the output end of the circulation module and the input end of the circulation module and is used for inputting the turnover signal of the circulation judgment comparison signal into the circulation module as a circulation continuation judging signal after receiving the circulation judgment starting signal so as to enable the circulation module to output the circulation judgment starting signal again when the circulation is not finished; And the circulation ending judgment module is connected with the output end of the signal delay and comparison module, the output end of the circulation module and the input end of the circulation module and is used for inputting the following signal of the circulation judgment comparison signal into the circulation module as the circulation ending judgment signal after receiving the circulation judgment starting signal so as to enable the circulation module to output the circulation response signal when the circulation is ended.
7. The configurable delay circuit of claim 6 wherein said signal delay and compare module comprises a second delay circuit, a counter, and a comparator, wherein, The input end of the second delay circuit is connected with the output end of the circulation module, the output end of the second delay circuit is connected with the first input end of the counter, the second input end of the counter is connected with the delay period configuration circuit, the output end of the counter is connected with the first input end of the comparator, the second input end of the comparator is connected with the delay period configuration circuit, and the output end of the comparator is respectively connected with the circulation continuation judging module and the circulation ending judging module; The second delay circuit comprises an even number of inverters connected in series, and is used for carrying out signal delay for a preset time length on the cycle judgment starting signal.
8. The configurable delay circuit of claim 7 wherein the cycle continue determination module comprises a second inverter and a third D flip-flop, wherein, The input end of the second inverter is connected with the output end of the comparator, the output end of the second inverter is connected with the data input end of the third D trigger, the clock input end of the third D trigger is connected with the output end of the second delay circuit, the reset input end of the third D trigger is connected with the output end of the circulation module, and the data output end of the third D trigger is connected with the input end of the circulation module; and the third D trigger is used for inputting the turning signal of the cycle judgment comparison signal into the cycle module as the cycle continuing judgment signal after receiving the delayed cycle judgment starting signal.
9. The configurable delay circuit of claim 7 wherein the end of cycle determination module comprises a fourth D flip-flop, wherein, The data input end of the fourth D trigger is connected with the output end of the comparator, the clock input end of the fourth D trigger is connected with the output end of the second delay circuit, the reset input end of the fourth D trigger is connected with the output end of the circulation module, and the data output end of the fourth D trigger is connected with the input end of the circulation module; The fourth D flip-flop is configured to input, after receiving the delayed cycle determination start signal, a following signal of the cycle determination comparison signal as the cycle end determination signal into the cycle module.
10. The configurable delay circuit of claim 1 wherein the loop module comprises a third inverter, a fourth inverter, a first AND OR gate, a second AND gate, a first AND gate, and a second AND gate, wherein, The input end of the third inverter is connected with the first output end of the circulation judging module, and the third inverter is used for receiving a circulation continuing judging signal output by the circulation judging module; The input end of the fourth inverter is connected with the second output end of the circulation judging module, and the fourth inverter is used for receiving the circulation ending judging signal output by the circulation judging module; the two input ends of the first AND OR gate are respectively connected with the output end of the cycle starting module and the output end of the second AND OR gate, and the two input ends of the second AND OR gate are respectively connected with the output end of the first AND OR gate and the output end of the fourth inverter; The three input ends of the first AND gate are respectively connected with the output end of the circulation starting module, the output end of the third inverter and the output end of the first AND gate, the output end of the first AND gate is connected with the input end of the circulation judging module, and the first AND gate is used for receiving a circulation starting signal and outputting the circulation judging starting signal; The two input ends of the second AND gate are respectively connected with the output end of the second AND gate and the output end of the fourth inverter, the output end of the second AND gate is connected with the input end of the circulation starting module, and the second AND gate is used for outputting the circulation response signal.

Description

Configurable delay circuit Technical Field The application relates to the technical field of asynchronous circuit design, in particular to a configurable delay circuit. Background In modern electronic system design, asynchronous circuits are effective means for solving the problems of clock distribution, power consumption, electromagnetic interference and the like because of the characteristic that global clock synchronization is not needed. However, in asynchronous circuits, the data transfer and processing between the modules requires a local control mechanism due to lack of global clock coordination. Delay control has become a critical issue in order to ensure smooth and accurate transfer of data between the different modules, and configurable delay circuits have developed. The configurable delay circuit is capable of dynamically adjusting the delay time under different conditions to optimize data transmission and system performance. In the prior art, one common design approach for configurable delay circuits is to insert a predetermined number of buffer cells on the signal line, which can introduce delay by increasing the signal propagation path length. However, in such a delay circuit, once the number of buffer units is determined, the delay time is fixed and cannot be dynamically adjusted as needed. In addition, this approach also results in a significant increase in circuit area where long delays are required, which is detrimental to system integration and cost control. Disclosure of Invention In view of the above, the embodiment of the present application provides a configurable delay circuit, which is mainly aimed at solving the technical problems that the delay time of the configurable delay circuit cannot be dynamically adjusted and the circuit structure is complex. According to one aspect of the present application, there is provided a configurable delay circuit comprising: The circulation starting module is connected with the signal source and used for receiving the signal to be delayed and outputting a circulation starting signal based on the signal to be delayed; the circulation module is connected with the output end of the circulation starting module and is used for outputting a circulation judging starting signal based on the circulation starting signal; The circulation judging module is connected with the output end of the circulation module and an external delay period configuration circuit, and is used for receiving a delay period signal, determining delay times based on the delay period signal, carrying out signal delay on the circulation judging start signal based on the delay times and outputting a circulation ending judging signal; the circulating module is connected with the output end of the circulating judging module and is also used for outputting a circulating response signal based on the circulating ending judging signal; the circulation starting module is connected with the output end of the circulation module, and is further used for resetting the circulation starting signal based on the circulation response signal, overturning the current signal and outputting a delayed signal. By means of the technical scheme, the configurable delay circuit provided by the embodiment of the application can realize the delay of the preset time length by configuring the delay periodic signal, so that the delay time length of the delay circuit can be dynamically changed under different application scenes, the delay circuit can be flexibly applied to various real-time working environments, and the reliability and accuracy of data transmission in an asynchronous circuit are improved. The circuit can improve the overall performance and response speed of the electronic system, reduces the complexity of circuit design, ensures that the circuit design is more flexible, can better meet diversified application requirements and environmental changes, and improves the reliability and user experience of the electronic system. Compared with the traditional delay circuit which inserts a stipulated number of buffer units in a signal line to realize delay operation, the circuit has more flexible application range and smaller circuit occupation area and circuit design complexity. The foregoing description is only an overview of the present application, and is intended to be implemented in accordance with the teachings of the present application in order that the same may be more clearly understood and to make the same and other objects, features and advantages of the present application more readily apparent. Drawings The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings: Fig. 1 is a schematic circuit diagram of a conf