Search

CN-122026871-A - Hysteresis comparator circuit and hysteresis comparator

CN122026871ACN 122026871 ACN122026871 ACN 122026871ACN-122026871-A

Abstract

The invention relates to the technical field of integrated circuits, and provides a hysteresis comparator circuit and a hysteresis comparator, wherein the hysteresis comparator circuit comprises a hysteresis comparator module, a first temperature compensation module and a second temperature compensation module; the hysteresis comparator module comprises a current mirror unit, an input stage circuit, a return difference introduction circuit and an output stage circuit, wherein the first temperature compensation module is connected with a ninth NMOS tube of the return difference introduction circuit, the second temperature compensation module is connected with an eighth NMOS tube of the return difference introduction circuit, the current mirror unit is used for providing zero temperature coefficient current for the hysteresis comparator module, and the input stage circuit comprises a forward input end and a reverse input end.

Inventors

  • XIA FAN
  • She Minjie

Assignees

  • 上海美仁半导体有限公司

Dates

Publication Date
20260512
Application Date
20241031

Claims (10)

  1. 1. The hysteresis comparator circuit is characterized by comprising a hysteresis comparator module (100), a first temperature compensation module (200) and a second temperature compensation module (300), wherein the hysteresis comparator module (100) comprises a current mirror unit (101), an input stage circuit (102), a return difference introduction circuit (103) and an output stage circuit (104), the first temperature compensation module (200) is connected with a ninth NMOS (NMOS) tube (9) of the return difference introduction circuit (103), the second temperature compensation module (300) is connected with an eighth NMOS tube (NMOS 8) of the return difference introduction circuit (103), the current mirror unit (101) is used for providing zero temperature coefficient current for the hysteresis comparator module (100), and the input stage circuit (102) comprises a forward input end and a reverse input end; When the input of the forward input end is smaller than the input of the reverse input end, a ninth NMOS tube (NMOS 9) of the return difference introduction circuit (103) is conducted, the first temperature compensation module (200) provides a first compensation current for the return difference introduction circuit (103) to form a forward return difference voltage, the voltage of the output stage circuit (104) is in a low level, and when the input of the forward input end is equal to the sum of the input of the reverse input end and the forward return difference voltage, the hysteresis comparator module (100) is turned over, and the voltage of the output stage circuit (104) is in a high level; When the input of the positive input end is larger than that of the reverse input end, an eighth NMOS tube (NMOS 8) of the return difference introduction circuit (103) is conducted, the second temperature compensation module (300) provides a second compensation current for the return difference introduction circuit (103) to form a negative return difference voltage, the voltage of the output stage circuit (104) is in a high level, and when the input of the positive input end is equal to the difference between the input of the reverse input end and the negative return difference voltage, the hysteresis comparator module (100) is turned over, and the voltage of the output stage circuit (104) is in a low level.
  2. 2. The hysteresis comparator circuit according to claim 1, wherein the current mirror unit (101) comprises a first NMOS transistor (NMOS 1), a second NMOS transistor (NMOS 2), a third NMOS transistor (NMOS 3), a fourth NMOS transistor (NMOS 4), and a first PMOS transistor (PMOS 1); The current mirror unit (101) provides zero temperature coefficient current by a band gap reference source, and a current mirror image is formed by the first NMOS tube (NMOS 1), the second NMOS tube (NMOS 2), the third NMOS tube (NMOS 3) and the fourth NMOS tube (NMOS 4).
  3. 3. The hysteresis comparator circuit according to claim 2, wherein the input stage circuit (102) comprises a third PMOS transistor (PMOS 3), a fourth PMOS transistor (PMOS 4), a fifth NMOS transistor (NMOS 5), a sixth NMOS transistor (NMOS 6), a seventh NMOS transistor (NMOS 7), and a second PMOS transistor (PMOS 2); The third PMOS tube (PMOS 3) and the fourth PMOS tube (PMOS 4) form a first operational amplifier input pair tube, the fifth NMOS tube (NMOS 5) and the sixth NMOS tube (NMOS 6) form a second operational amplifier input pair tube, the second PMOS tube (PMOS 2) is used as a tail current source of the current mirror unit (101) for providing input current for the first operational amplifier input pair tube, the seventh NMOS tube (NMOS 7) is used as a tail current source of the current mirror unit (101) for providing input current for the second operational amplifier input pair tube, the grid electrode of the third PMOS tube (PMOS 3) and the grid electrode of the fifth NMOS tube (NMOS 5) are connected with the reverse input end of the hysteresis comparator circuit, and the grid electrode of the fourth PMOS tube (PMOS 4) and the grid electrode of the sixth NMOS tube (NMOS 6) are connected with the forward input end of the hysteresis comparator circuit.
  4. 4. A hysteresis comparator circuit according to claim 3, characterized in that said return difference introducing circuit (103) comprises said eighth NMOS transistor (NMOS 8) and said ninth NMOS transistor (NMOS 9); The source electrode of the ninth NMOS tube (NMOS 9) is connected with the first temperature compensation module (200), the grid control signal of the ninth NMOS tube (NMOS 9) is an inverse signal voutb of an output voltage vout, the drain electrode of the ninth NMOS tube (NMOS 9) is connected with the drain electrode of the third PMOS tube (PMOS 3), the drain electrode of the eighth NMOS tube (NMOS 8) is connected with the second temperature compensation module (300), the grid control signal of the eighth NMOS tube (NMOS 8) is the output voltage vout, and the source electrode of the eighth NMOS tube (NMOS 8) is connected with the drain electrode of the third PMOS tube (PMOS 3).
  5. 5. The hysteresis comparator circuit according to claim 4, wherein the output stage circuit (104) comprises a fifth PMOS transistor (PMOS 5), a sixth PMOS transistor (PMOS 6), a seventh PMOS transistor (PMOS 7), an eighth PMOS transistor (PMOS 8), a ninth PMOS transistor (PMOS 9), a tenth PMOS transistor (PMOS 10), an eleventh PMOS transistor (PMOS 11), a twelfth PMOS transistor (PMOS 12), a thirteenth PMOS transistor (PMOS 13), a fourteenth PMOS transistor (PMOS 14), a fifteenth PMOS transistor (PMOS 15), a tenth NMOS transistor (NMOS 10), an eleventh NMOS transistor (NMOS 11), a twelfth NMOS transistor (NMOS 12), a thirteenth NMOS transistor (NMOS 13), a fourteenth NMOS transistor (NMOS 14), a fifteenth NMOS transistor (NMOS 15), a sixteenth NMOS transistor (NMOS 16), a seventeenth NMOS transistor (NMOS 17), a nineteenth NMOS transistor (NMOS 18), a nineteenth NMOS transistor (PMOS 19), a twenty-eighth NMOS transistor (NMOS 20), a source of the thirteenth NMOS transistor (NMOS 12) being grounded, a NMOS of the thirteenth NMOS transistor (NMOS 14) being connected to the drain of the thirteenth transistor (NMOS) and the thirteenth NMOS transistor (NMOS 13), the source of the thirteenth transistor (NMOS) being connected to the drain of the thirteenth transistor (NMOS 13); When the input of the forward input end is smaller than the input of the reverse input end, the current flowing through the drain electrode of the thirteenth NMOS tube (NMOS 13) is the difference between the current flowing through the drain electrode of the third PMOS tube (PMOS 3) and the first compensation current provided by the first temperature compensation module (200) so as to obtain a forward return difference; When the input of the positive input end is larger than the input of the negative input end, the current flowing through the drain electrode of the thirteenth NMOS tube (NMOS 13) is the sum of the current flowing through the drain electrode of the third PMOS tube (PMOS 3) and the second compensation current provided by the second temperature compensation module (300) so as to obtain a negative return difference.
  6. 6. The hysteresis comparator circuit of claim 5, wherein the first temperature compensation module (200) comprises a nineteenth PMOS transistor (PMOS 19), a twentieth PMOS transistor (PMOS 20), a twenty first PMOS transistor (PMOS 21), a twenty first NMOS transistor (NMOS 21), a twenty second NMOS transistor (NMOS 22), a first resistor, a second resistor, a third resistor, and a first operational amplifier, wherein the first resistor, the second resistor, and the third resistor are all positive temperature coefficient resistors; The gate voltages of the nineteenth PMOS tube (PMOS 19), the twenty first PMOS tube (PMOS 20) and the twenty first PMOS tube (PMOS 21) are clamped by the output end of the first operational amplifier, the reverse input end of the first operational amplifier is connected with the emitters of PNP triodes with the parallel number of 1 and the second resistor, the forward input end of the first operational amplifier is connected with the first resistor and the third resistor, and the first resistor is connected with the emitters of the PNP triodes with the parallel number of m.
  7. 7. The hysteresis comparator circuit of claim 6 wherein the current flowing through the first resistor is a first positive temperature coefficient current and the current flowing through the second resistor and the third resistor is a first negative temperature coefficient current; And the first positive temperature coefficient current is overlapped with the first negative temperature coefficient current to obtain the first compensation current.
  8. 8. The hysteresis comparator circuit of claim 5, wherein the second temperature compensation module (300) comprises a sixteenth PMOS transistor (PMOS 16), a seventeenth PMOS transistor (PMOS 17), an eighteenth PMOS transistor (PMOS 18), a fourth resistor, a fifth resistor, a sixth resistor, and a second operational amplifier, wherein the fourth resistor, the fifth resistor, and the sixth resistor are positive temperature coefficient resistors; The gate voltages of the sixteenth PMOS transistor (PMOS 16), the seventeenth PMOS transistor (PMOS 17) and the eighteenth PMOS transistor (PMOS 18) are clamped by the output terminal of the second operational amplifier, the reverse input terminal of the second operational amplifier is connected with the emitters of PNP triodes with the number of 1 in parallel and the fifth resistor, the forward input terminal of the second operational amplifier is connected with the fourth resistor and the sixth resistor, and the fourth resistor is connected with the emitters of PNP triodes with the number of m in parallel.
  9. 9. The hysteresis comparator circuit according to claim 8, wherein the current flowing through the fourth resistor is a second positive temperature coefficient current and the current flowing through the fifth resistor and the sixth resistor is a second negative temperature coefficient current; and the second positive temperature coefficient current is overlapped with the second negative temperature coefficient current to obtain the second compensation current.
  10. 10. A hysteresis comparator comprising a hysteresis comparator circuit according to any one of claims 1-9.

Description

Hysteresis comparator circuit and hysteresis comparator Technical Field The present invention relates to the field of integrated circuits, and more particularly, to a hysteresis comparator circuit and a hysteresis comparator. Background The hysteresis comparator is a comparator with hysteresis loop transmission characteristics, compared with a single-threshold comparator with only one fixed reference voltage, the hysteresis comparator has two comparison references which change along with the output state, and the output voltage of the hysteresis comparator can not change suddenly after a period of time when the input voltage reaches the threshold voltage, so the hysteresis comparator is widely applied to circuits with higher stability requirements, but the hysteresis comparator has the problem of larger influence of temperature. In the related art, a complex adjusting circuit is usually required to be additionally added to realize the return difference adjustment of the hysteresis comparator, which leads to the increase of the whole area and the power consumption of the integrated circuit, and the application scene of the inverter structure used in the related art is not comprehensive. Therefore, how to improve the temperature drift of hysteresis comparator return difference has become a problem to be solved. Disclosure of Invention The present invention aims to solve at least one of the technical problems in the related art to some extent. The first object of the invention is to provide a hysteresis comparator circuit, which comprises a hysteresis comparator module, a first temperature compensation module and a second temperature compensation module, wherein the hysteresis comparator module comprises a current mirror unit, an input stage circuit, a return difference introduction circuit and an output stage circuit, the first temperature compensation module is connected with a ninth NMOS tube of the return difference introduction circuit, the second temperature compensation module is connected with an eighth NMOS tube of the return difference introduction circuit, the current mirror unit is used for providing zero temperature coefficient current for the hysteresis comparator module, the input stage circuit comprises a positive input end and a reverse input end, when the input of the positive input end is smaller than the input of the reverse input end, the ninth NMOS tube of the return difference introduction circuit is conducted, the first temperature compensation module provides a first compensation current for the return difference introduction circuit to form a positive return difference voltage, the voltage of the output stage circuit is at a low level, when the input of the positive input end is equal to the sum of the input of the reverse input end and the positive return difference voltage, the hysteresis comparator module is turned over at a high level, when the input of the positive input end is greater than the input of the reverse input end, the return difference introduction circuit is equal to the negative input of the return difference voltage, the eighth NMOS tube is turned over, the return difference introduction circuit is formed at the positive input end and the negative return difference voltage, the second temperature compensation module is turned over at the positive input end, the return voltage is equal to the negative input of the return voltage. In addition, the hysteresis comparator circuit according to the above embodiment of the present invention may have the following additional technical features: The current mirror unit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube and a first PMOS tube, wherein the current mirror unit provides zero temperature coefficient current by a band gap reference source and is a current mirror image formed by the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube. The input stage circuit comprises a third PMOS tube, a fourth PMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube and a second PMOS tube, wherein the third PMOS tube and the fourth PMOS tube form a first operational amplifier input pair tube, the fifth NMOS tube and the sixth NMOS tube form a second operational amplifier input pair tube, the second PMOS tube is used as a tail current source of a current mirror unit to provide input current for the first operational amplifier input pair tube, the seventh NMOS tube is used as a tail current source of the current mirror unit to provide input current for the second operational amplifier input pair tube, a grid electrode of the third PMOS tube and a grid electrode of the fifth NMOS tube are connected with a reverse input end of the hysteresis comparator circuit, and a grid electrode of the fourth PMOS tube and a grid electrode of the sixth NMOS tube are connected with a forward input end of the hysteresis comparator circuit. As an alternative embodiment, th