CN-122026872-A - Clock generation circuit of comparator and analog-to-digital converter

CN122026872ACN 122026872 ACN122026872 ACN 122026872ACN-122026872-A

Abstract

The invention provides a clock generation circuit and an analog-to-digital converter of a comparator, wherein a grid electrode of a first PMOS tube is connected with a sampling clock, grid electrodes of a fourth P tube and a fifth P tube are respectively connected with a first output end and a second output end of the comparator, source electrodes of the first P tube, the fourth P tube and the fifth P tube are connected with a power supply, a drain electrode of the first P tube is connected with a source electrode of the second P tube, a drain electrode of the second P tube is connected with a drain electrode of a thirteenth N tube, grid electrodes of the second P tube, drain electrodes of the fifth P tube, grid electrodes of the thirteenth N tube and a second end of the delay pull-down unit are connected with a first point, and a drain lead-out wiring terminal of the second P tube is connected with an output end of the clock generation circuit and is connected with a clock input port of the comparator. By optimizing the circuit structure, the loop time corresponding to the clock of the comparator can be greatly shortened, so that the running speed of the comparator and the analog-to-digital converter is improved.

Inventors

YAN LI
ZENG LING
WANG JIAXIN
LEI RUI

Assignees

厦门芯和美半导体有限公司

Dates

Publication Date: 20260512
Application Date: 20260130

Claims (10)

1. The clock generation circuit of the comparator is characterized by comprising a first PMOS tube (M1), a second PMOS tube (M2), a fourth PMOS tube (M4), a fifth PMOS tube (M5), a thirteenth NMOS tube (M13) and a delay pull-down unit; The grid electrode of the first PMOS tube (M1) is used for being connected with a sampling Clock (CLKS), the grid electrode of the fourth PMOS tube (M4) is used for being connected with a first output end (Q) of the comparator, and the grid electrode of the fifth PMOS tube (M5) is used for being connected with a second output end (QB) of the comparator; The source electrode of the first PMOS tube (M1), the source electrode of the fourth PMOS tube (M4) and the source electrode of the fifth PMOS tube (M5) are connected to a power supply (VDD), the drain electrode of the first PMOS tube (M1) is connected to the source electrode of the second PMOS tube (M2), and the drain electrode of the second PMOS tube (M2) is connected to the drain electrode of the thirteenth NMOS tube (M13); The grid electrode of the second PMOS tube (M2), the drain electrode of the fourth PMOS tube (M4), the drain electrode of the fifth PMOS tube (M5), the grid electrode of the thirteenth NMOS tube (M13) and the first end of the delay pull-down unit are all connected to a first point (VA), and the source electrode of the thirteenth NMOS tube (M13) and the second end of the delay pull-down unit are grounded; The drain electrode lead-out wiring terminal (VC) of the second PMOS tube (M2) is connected with the output end of the clock generation circuit and is used for being connected with the clock input port of the comparator.
2. A clock generation circuit of a comparator according to claim 1, wherein the first point (VA) is at a low level when the sampling Clock (CLKS) is switched from high to low, the first PMOS transistor (M1) and the second PMOS transistor (M2) are turned on, the drain of the second PMOS transistor (M2) is pulled high, the clock generation circuit outputting a high level clock signal to the comparator; The comparator starts working after receiving a high-level clock signal, and after single comparison is completed, any output end is controlled to output a low-level signal, the fourth PMOS tube (M4) or the fifth PMOS tube (M5) is switched into a conducting state, a first point (VA) is pulled high, the second PMOS tube (M2) is turned off, the thirteenth NMOS tube (M13) is conducted, so that the drain electrode of the second PMOS tube (M2) is pulled down, the clock generation circuit outputs a low-level clock signal to the comparator, and the comparator stops working; the delay pull-down unit is switched to a conducting state after a preset delay time length after the first point (VA) is pulled up, so that the first point (VA) is pulled down.
3. The clock generation circuit of the comparator according to claim 2, wherein the clock generation circuit further includes a first AND operator (AND 1); The first input end of the first AND operator (AND 1) is connected with the wiring terminal (VC), the second input end of the first AND operator (AND 1) is used for being connected with a first switching signal (ADC_EN), AND the output end of the first AND operator (AND 1) is used as the output end of the clock generation circuit AND is used for being connected with the clock input port of the comparator; The first switching signal (adc_en) is configured such that the clock generation circuit normally outputs a clock signal when the first switching signal (adc_en) is high, and the clock generation circuit keeps outputting a low level clock signal when the first switching signal (adc_en) is low.
4. A clock generation circuit of a comparator as claimed in claim 2, characterized in that the clock generation circuit further comprises a third NMOS transistor (M3); The grid electrode of the third NMOS tube (M3), the drain electrode of the third NMOS tube (M3) is connected with the drain electrode of the second PMOS tube, and the source electrode of the third NMOS tube (M3) is grounded.
5. A clock generation circuit of a comparator as claimed in claim 2, characterized in that the clock generation circuit further comprises a sixth NMOS transistor (M6); The grid electrode of the sixth NMOS tube (M6) is used for being connected with the sampling Clock (CLKS), the drain electrode of the sixth NMOS tube (M6) is connected with the first point (VA), and the source electrode of the sixth NMOS tube (M6) is grounded.
6. The clock generation circuit of the comparator according to any one of claims 1 to 5, wherein the delay pull-down unit includes a seventh NMOS transistor (M7), an eleventh PMOS transistor (M11), a twelfth NMOS transistor (M12), an inverter, a delay, AND a second AND operator (AND 2); The source electrode of the eleventh PMOS tube (M11) is connected with a power supply (VDD), the drain electrode of the seventh NMOS tube (M7) and the grid electrode of the eleventh PMOS tube (M11) are connected with the first point (VA), the drain electrode of the eleventh PMOS tube (M11) and the input end of the delayer are connected with the drain electrode of the twelfth NMOS tube (M12), the output end of the delayer is connected with the input end (VB) of the reverser, and the output end of the reverser is connected with the grid electrode of the seventh NMOS tube (M7); the source electrode of the seventh NMOS tube (M7) AND the source electrode of the twelfth NMOS tube (M12) are grounded, the first input end of the second AND operator (AND 2) is connected to the first point (VA), the second input end of the second AND operator (AND 2) is connected to the input end (VB) of the reverser, AND the output end of the second AND operator (AND 2) is connected to the grid electrode of the twelfth NMOS tube (M12).
7. The clock generation circuit of the comparator as claimed in claim 6, wherein the inverter comprises a ninth PMOS transistor (M9) and a tenth NMOS transistor (M10); The source electrode of the ninth PMOS tube (M9) is connected to a power supply (VDD), the drain electrode of the ninth PMOS tube (M9) is connected to the drain electrode of the tenth NMOS tube (M10), and the source electrode of the drain electrode is grounded; The input end of the inverter is led out between the grid electrode of the ninth PMOS tube (M9) and the grid electrode of the tenth NMOS tube (M10); And the output end of the inverter is led out between the drain electrode of the ninth PMOS tube (M9) and the drain electrode of the tenth NMOS tube (M10).
8. The clock generation circuit of the comparator as claimed in claim 7, wherein the inverter comprises an eighth PMOS tube (M8); The source electrode of the eighth PMOS tube (M8) is connected to a power supply (VDD), the drain electrode of the eighth PMOS tube (M8) is connected to the source electrode of the ninth PMOS tube (M9), and the grid electrode of the eighth PMOS tube (M8) is used for being connected to a second switching signal (EN); When the sampling Clock (CLKS) is low, the second switching signal (EN) is switched from low level to high level after the comparator has completed the comparison operation of the current round.
9. The clock generation circuit of claim 6, wherein the delay is a delay with an adjustable delay duration.
10. An analog-to-digital converter, characterized by a clock generation circuit comprising a comparator as claimed in any one of claims 1-9.

Description

Clock generation circuit of comparator and analog-to-digital converter Technical Field The present invention relates to the field of integrated circuits, and in particular, to a clock generation circuit and an analog-to-digital converter of a comparator. Background With the rapid development of the fields of 5G communication, high-speed data acquisition, radar systems, scientific instruments and the like, the performance requirements of analog-to-digital converters (ADC for short) are increasingly stringent, and particularly, better balance needs to be achieved in terms of sampling speed, precision and power consumption. The need for a partial analog-to-digital converter to perform N (N is the number of analog-to-digital converter bits) comparison operations per conversion cycle makes it a significant challenge in pursuing ultra-high speed (e.g., sample rate >1 GS/s) applications. The speed of the analog-to-digital converter is limited by the speed of the comparator therein, and the speed of the comparator in the analog-to-digital converter is limited by its corresponding clock, so a new comparator clock generation circuit is needed to solve the speed bottleneck problem. Disclosure of Invention The present invention is directed to a clock generation circuit and an analog-to-digital converter for a comparator, so as to improve the above-mentioned problems. In order to achieve the above object, the technical scheme adopted by the embodiment of the invention is as follows: in a first aspect, an embodiment of the present invention provides a clock generating circuit of a comparator, where the clock generating circuit includes a first PMOS transistor, a second PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a thirteenth NMOS transistor, and a delay pull-down unit; The grid electrode of the first PMOS tube is used for being connected with a sampling clock, the grid electrode of the fourth PMOS tube is used for being connected with the first output end of the comparator, and the grid electrode of the fifth PMOS tube is used for being connected with the second output end of the comparator; the source electrode of the first PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are connected to a power supply, the drain electrode of the first PMOS tube is connected to the source electrode of the second PMOS tube, and the drain electrode of the second PMOS tube is connected to the drain electrode of the thirteenth NMOS tube; The grid electrode of the second PMOS tube, the drain electrode of the fourth PMOS tube, the drain electrode of the fifth PMOS tube, the grid electrode of the thirteenth NMOS tube and the first end of the delay pull-down unit are all connected to a first point, and the source electrode of the thirteenth NMOS tube and the second end of the delay pull-down unit are grounded; and a drain electrode lead-out wiring terminal of the second PMOS tube is connected to the output end of the clock generation circuit and is used for being connected with a clock input port of the comparator. In a second aspect, an embodiment of the present invention provides an analog-to-digital converter, including the clock generating circuit of the comparator. Compared with the prior art, the clock generation circuit and the analog-to-digital converter of the comparator provided by the embodiment of the invention comprise a first PMOS tube, a second PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a thirteenth NMOS tube and a delay pull-down unit, wherein the grid electrode of the first PMOS tube is used for being connected with a sampling clock, the grid electrode of the fourth PMOS tube is used for being connected with a first output end of the comparator, the grid electrode of the fifth PMOS tube is used for being connected with a second output end of the comparator, the source electrode of the first PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are connected to a power supply, the drain electrode of the first PMOS tube is connected to the source electrode of the second PMOS tube, the drain electrode of the second PMOS tube is connected to the drain electrode of the thirteenth NMOS tube, the drain electrode of the fourth PMOS tube, the grid electrode of the thirteenth NMOS tube and the first end of the delay pull-down unit are connected to a first point, the source electrode of the thirteenth tube and the second end of the delay pull-down unit are grounded, and the drain terminal of the second PMOS tube is connected to the output end of the comparator for being connected to the input port of the clock generation circuit. By optimizing the circuit structure, the loop time corresponding to the clock of the comparator can be greatly shortened, so that the running speed of the comparator and the analog-to-digital converter is improved. In order to make the above objects, features and advantages of t