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CN-122026873-A - Pulse width modulation signal generating circuit

CN122026873ACN 122026873 ACN122026873 ACN 122026873ACN-122026873-A

Abstract

The application provides a pulse width modulation signal generating circuit which is applied to the technical field of integrated circuits and comprises an integrating circuit, a first comparison circuit, a second comparison circuit and a control circuit, wherein the integrating circuit charges a first capacitor when the first comparison circuit outputs a first level signal, discharges through the first capacitor when the first comparison circuit outputs a second level signal, the first comparison circuit outputs the first level signal when the voltage of the first capacitor is lower than a first reference voltage, outputs the second level signal when the voltage of the first capacitor is higher than a second reference voltage, the control circuit outputs the first reference voltage when the first comparison circuit outputs the first level signal, outputs the second reference voltage when the first comparison circuit outputs the second level signal, and the second comparison circuit outputs a pulse width modulation signal according to the reference voltage when the first capacitor is charged or discharged. The output of the pulse width modulation signal can be realized without a singlechip circuit, and the research and development cost is reduced.

Inventors

  • Pi Changkun
  • HUANG ZHENGHAO

Assignees

  • 曼德电子电器有限公司

Dates

Publication Date
20260512
Application Date
20260108

Claims (10)

  1. 1. A pulse width modulation signal generating circuit is characterized by comprising an integrating circuit, a first comparison circuit, a second comparison circuit and a control circuit, wherein, The integrating circuit comprises a first capacitor, and the integrating circuit is configured to charge the first capacitor when the first comparing circuit outputs a first level signal and discharge through the first capacitor when the first comparing circuit outputs a second level signal; The first input end of the first comparison circuit is electrically connected with the first capacitor, and the second input end of the first comparison circuit is electrically connected with the control circuit and is used for outputting the first level signal when the voltage of the first capacitor is lower than a first reference voltage and outputting the second level signal when the voltage of the first capacitor is higher than a second reference voltage; the control circuit is configured to output the first reference voltage when the first comparison circuit outputs the first level signal, and to output a second reference voltage when the first comparison circuit outputs the second level signal; The first input end of the second comparison circuit is connected with one end of the first capacitor, the second input end of the second comparison circuit is connected with a preset reference voltage node, and the second comparison circuit is configured to output a pulse width modulation signal according to a preset reference voltage when the first capacitor is charged or discharged.
  2. 2. The pulse width modulated signal generation circuit of claim 1, wherein the first comparison circuit comprises: a first resistor, a second capacitor, a first comparison piece and a third capacitor, wherein, One end of the first resistor and one end of the second capacitor are electrically connected with the inverting input end of the first comparison piece and the control circuit, and the other end of the first resistor and the other end of the second capacitor are connected with a grounding node; the non-inverting input end of the first comparison piece is electrically connected with one end of the first capacitor; One end of the third capacitor is electrically connected with the first input end of the first comparison piece and the power supply node respectively, the other end of the third capacitor is electrically connected with the grounding node, and the second input end of the first comparison piece is connected with the grounding node.
  3. 3. The pulse width modulated signal generating circuit of claim 2, wherein the second comparison circuit comprises: A second comparison part, a second resistor and a fourth capacitor, wherein, The non-inverting input end of the second comparison piece is electrically connected with a preset reference voltage node, and the inverting input end of the second comparison piece is electrically connected with one end of the second resistor; the other end of the second resistor is electrically connected with one end of the first capacitor; one end of the fourth capacitor is electrically connected with the first input end of the second comparison part and the power supply node respectively, the second input end of the second comparison part is electrically connected with the grounding node, and the other end of the fourth capacitor is electrically connected with the grounding node.
  4. 4. The pulse width modulated signal generation circuit of claim 3, wherein the integration circuit further comprises: a third resistor and a charge-discharge switching circuit, wherein, One end of the third resistor is connected with a first connection node between one end of the first capacitor and the other end of the second resistor, and the other end of the third resistor is electrically connected with the first end of the charge-discharge switch circuit; The second end of the charge-discharge switch circuit is connected with the power supply node, the third end of the charge-discharge switch circuit is connected with the grounding node, and the fourth end of the charge-discharge switch circuit is electrically connected with the control circuit.
  5. 5. The pulse width modulated signal generating circuit of claim 4, wherein the charge-discharge switching circuit comprises: a first MOS tube and a first voltage dividing resistor circuit, The drain electrode of the first MOS tube is connected with a second connection node between the other end of the third resistor and the first end of the first voltage dividing resistor circuit, the source electrode of the first MOS tube is connected with the grounding node, and the grid electrode of the first MOS tube is connected with the control circuit; the second end of the first voltage dividing resistor circuit is electrically connected with the power supply node, and the third end of the first voltage dividing resistor circuit is electrically connected with the grounding node.
  6. 6. The pulse width modulated signal generation circuit of claim 5, wherein the first voltage dividing resistor circuit comprises: a fourth resistor and a fifth resistor, wherein, One end of the fourth resistor is connected with the power supply node, and the other end of the fourth resistor is electrically connected with a third connecting node between one end of the fifth resistor and the second connecting node respectively; the other end of the fifth resistor is connected with the grounding node.
  7. 7. The pulse width modulated signal generation circuit of claim 6, wherein the control circuit comprises: A second MOS tube, a sixth resistor, a seventh resistor and a second voltage-dividing resistor circuit, wherein, One end of the sixth resistor is electrically connected with the output end of the first amplifying piece, and the other end of the sixth resistor is electrically connected with a fourth connecting node among the grid electrode of the second MOS tube, one end of the seventh resistor and the grid electrode of the first MOS tube; the other end of the seventh resistor is connected with the grounding node; The drain electrode of the second MOS tube is electrically connected with the first end of the second voltage-dividing resistor circuit, and the source electrode of the second MOS tube is electrically connected with the grounding node; The second end of the second voltage dividing resistor circuit is electrically connected with the power supply node, and the third end of the second voltage dividing resistor circuit is connected with the inverting input end of the first comparison piece.
  8. 8. The pulse width modulated signal generation circuit of claim 7, wherein the second voltage divider resistor circuit comprises: eighth and ninth resistors, wherein, One end of the eighth resistor is connected with the drain electrode of the second MOS tube, and the other end of the eighth resistor is connected with a fifth connecting node between one end of the ninth resistor and the inverting input end of the first comparison piece; the other end of the ninth resistor is electrically connected with the power supply node.
  9. 9. The pulse width modulated signal generation circuit of claim 8, wherein the control circuit comprises: And one end of the tenth resistor is connected with the second connection node, and the other end of the tenth resistor is connected with a third connection node between the other end of the fourth resistor and one end of the fifth resistor.
  10. 10. The pulse width modulated signal generating circuit of any of claims 1-9, wherein the first and second comparators are dual path operational amplifiers and the first and second MOS transistors are N-channel enhancement field effect transistors.

Description

Pulse width modulation signal generating circuit Technical Field The present application relates to the field of integrated circuit technology, and more particularly to pulse width modulated signal generation circuits in the field of integrated circuit technology. Background The current scheme for realizing the pulse width modulation function of the automobile lighting product by adopting the MCU has the problems of higher overall research and development cost and resource waste of the product. Disclosure of Invention The application provides a pulse width modulation signal generation circuit, which solves the problems of high material and research and development costs of a conventional pulse width modulation signal output circuit adopting a single-chip microcomputer circuit. The application provides a pulse width modulation signal generation circuit method, which comprises an integrating circuit, a first comparison circuit, a second comparison circuit and a control circuit, wherein the integrating circuit comprises a first capacitor, the integrating circuit is configured to charge the first capacitor when the first comparison circuit outputs a first level signal and discharge through the first capacitor when the first comparison circuit outputs a second level signal, a first input end of the first comparison circuit is electrically connected with the first capacitor, a second input end of the first comparison circuit is electrically connected with the control circuit and is used for outputting the first level signal when the voltage of the first capacitor is lower than a first reference voltage, the second level signal is output when the voltage of the first capacitor is higher than a second reference voltage, the control circuit is configured to output the first reference voltage when the first comparison circuit outputs the first level signal and discharge through the first capacitor when the first comparison circuit outputs the second level signal, and the first input end of the first comparison circuit is connected with the first reference voltage or the second reference voltage is connected with the first input end of the first comparison circuit. In some possible implementations, the first comparison circuit comprises a first resistor, a second capacitor, a first comparison piece and a third capacitor, wherein one end of the first resistor and one end of the second capacitor are electrically connected with the inverting input end of the first comparison piece and the control circuit, the other end of the first resistor and the other end of the second capacitor are electrically connected with a grounding node, the non-inverting input end of the first comparison piece is electrically connected with one end of the first capacitor, one end of the third capacitor is electrically connected with the first input end of the first comparison piece and a power supply node respectively, the other end of the third capacitor is electrically connected with a grounding node, and the second input end of the first comparison piece is connected with the grounding node. According to the technical scheme, the voltage of the first capacitor is used as a trigger condition to control the charge and discharge of the integrating circuit by utilizing the level overturning characteristic of the first comparison piece, and the first resistor and the second capacitor can inhibit noise of an input signal. In some possible implementations, the second comparison circuit comprises a second comparison piece, a second resistor and a fourth capacitor, wherein the non-inverting input end of the second comparison piece is electrically connected with a preset reference voltage node, the inverting input end of the second comparison piece is electrically connected with one end of the second resistor, the other end of the second resistor is electrically connected with one end of the first capacitor, one end of the fourth capacitor is respectively electrically connected with the first input end of the second comparison piece and the power supply node, the second input end of the second comparison piece is electrically connected with the grounding node, and the other end of the fourth capacitor is electrically connected with the grounding node. Through the technical scheme, the triangular wave generated by the integrating circuit is compared with the preset reference voltage in real time by the second comparison circuit, the high-low level signal is output through level inversion and is directly converted into the PWM waveform, the second resistor R8 plays roles of isolation and voltage division, the fourth capacitor can realize filtering, and the association of the PWM duty ratio and the reference voltage is realized through the preset reference voltage node, so that the PWM duty ratio adjustment is realized. In some possible implementations, the integrating circuit further comprises a third resistor and a charge-discharge switch circuit, whe